1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung SoC series UFS host controller 8 9maintainers: 10 - Alim Akhtar <alim.akhtar@samsung.com> 11 12description: | 13 Each Samsung UFS host controller instance should have its own node. 14 15properties: 16 compatible: 17 enum: 18 - google,gs101-ufs 19 - samsung,exynos7-ufs 20 - samsung,exynosautov9-ufs 21 - samsung,exynosautov9-ufs-vh 22 - tesla,fsd-ufs 23 24 reg: 25 items: 26 - description: HCI register 27 - description: vendor specific register 28 - description: unipro register 29 - description: UFS protector register 30 31 reg-names: 32 items: 33 - const: hci 34 - const: vs_hci 35 - const: unipro 36 - const: ufsp 37 38 clocks: 39 minItems: 2 40 items: 41 - description: ufs link core clock 42 - description: unipro main clock 43 - description: fmp clock 44 - description: ufs aclk clock 45 - description: ufs pclk clock 46 - description: sysreg clock 47 48 clock-names: 49 minItems: 2 50 items: 51 - const: core_clk 52 - const: sclk_unipro_main 53 - const: fmp 54 - const: aclk 55 - const: pclk 56 - const: sysreg 57 58 phys: 59 maxItems: 1 60 61 phy-names: 62 const: ufs-phy 63 64 samsung,sysreg: 65 $ref: /schemas/types.yaml#/definitions/phandle-array 66 items: 67 - items: 68 - description: phandle to FSYSx sysreg node 69 - description: offset of the control register for UFS io coherency setting 70 description: 71 Phandle and offset to the FSYSx sysreg for UFS io coherency setting. 72 73 dma-coherent: true 74 75required: 76 - compatible 77 - reg 78 - phys 79 - phy-names 80 - clocks 81 - clock-names 82 83allOf: 84 - $ref: ufs-common.yaml 85 - if: 86 properties: 87 compatible: 88 contains: 89 const: google,gs101-ufs 90 91 then: 92 properties: 93 clocks: 94 minItems: 6 95 96 clock-names: 97 minItems: 6 98 99 else: 100 properties: 101 clocks: 102 maxItems: 2 103 104 clock-names: 105 maxItems: 2 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 #include <dt-bindings/clock/exynos7-clk.h> 113 114 ufs: ufs@15570000 { 115 compatible = "samsung,exynos7-ufs"; 116 reg = <0x15570000 0x100>, 117 <0x15570100 0x100>, 118 <0x15571000 0x200>, 119 <0x15572000 0x300>; 120 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 121 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&clock_fsys1 ACLK_UFS20_LINK>, 123 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; 124 clock-names = "core_clk", "sclk_unipro_main"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 127 phys = <&ufs_phy>; 128 phy-names = "ufs-phy"; 129 }; 130... 131