1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SC7180 and Other SoCs UFS Controllers 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12# Select only our matches, not all jedec,ufs-2.0 13select: 14 properties: 15 compatible: 16 contains: 17 enum: 18 - qcom,msm8998-ufshc 19 - qcom,qcs8300-ufshc 20 - qcom,sa8775p-ufshc 21 - qcom,sc7180-ufshc 22 - qcom,sc7280-ufshc 23 - qcom,sc8180x-ufshc 24 - qcom,sc8280xp-ufshc 25 - qcom,sm8250-ufshc 26 - qcom,sm8350-ufshc 27 - qcom,sm8450-ufshc 28 - qcom,sm8550-ufshc 29 required: 30 - compatible 31 32properties: 33 compatible: 34 items: 35 - enum: 36 - qcom,msm8998-ufshc 37 - qcom,qcs8300-ufshc 38 - qcom,sa8775p-ufshc 39 - qcom,sc7180-ufshc 40 - qcom,sc7280-ufshc 41 - qcom,sc8180x-ufshc 42 - qcom,sc8280xp-ufshc 43 - qcom,sm8250-ufshc 44 - qcom,sm8350-ufshc 45 - qcom,sm8450-ufshc 46 - qcom,sm8550-ufshc 47 - const: qcom,ufshc 48 - const: jedec,ufs-2.0 49 50 reg: 51 maxItems: 1 52 53 reg-names: 54 items: 55 - const: std 56 57 clocks: 58 minItems: 7 59 maxItems: 8 60 61 clock-names: 62 minItems: 7 63 items: 64 - const: core_clk 65 - const: bus_aggr_clk 66 - const: iface_clk 67 - const: core_clk_unipro 68 - const: ref_clk 69 - const: tx_lane0_sync_clk 70 - const: rx_lane0_sync_clk 71 - const: rx_lane1_sync_clk 72 73 qcom,ice: 74 $ref: /schemas/types.yaml#/definitions/phandle 75 description: phandle to the Inline Crypto Engine node 76 77required: 78 - compatible 79 - reg 80 81allOf: 82 - $ref: qcom,ufs-common.yaml 83 84 - if: 85 properties: 86 compatible: 87 contains: 88 enum: 89 - qcom,sc7180-ufshc 90 then: 91 properties: 92 clocks: 93 maxItems: 7 94 clock-names: 95 maxItems: 7 96 else: 97 properties: 98 clocks: 99 minItems: 8 100 clock-names: 101 minItems: 8 102 103unevaluatedProperties: false 104 105examples: 106 - | 107 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 108 #include <dt-bindings/clock/qcom,rpmh.h> 109 #include <dt-bindings/gpio/gpio.h> 110 #include <dt-bindings/interconnect/qcom,sm8450.h> 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 113 soc { 114 #address-cells = <2>; 115 #size-cells = <2>; 116 117 ufs@1d84000 { 118 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 119 "jedec,ufs-2.0"; 120 reg = <0x0 0x01d84000 0x0 0x3000>; 121 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 122 phys = <&ufs_mem_phy_lanes>; 123 phy-names = "ufsphy"; 124 lanes-per-direction = <2>; 125 #reset-cells = <1>; 126 resets = <&gcc GCC_UFS_PHY_BCR>; 127 reset-names = "rst"; 128 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 129 130 vcc-supply = <&vreg_l7b_2p5>; 131 vcc-max-microamp = <1100000>; 132 vccq-supply = <&vreg_l9b_1p2>; 133 vccq-max-microamp = <1200000>; 134 135 power-domains = <&gcc UFS_PHY_GDSC>; 136 iommus = <&apps_smmu 0xe0 0x0>; 137 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 138 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 139 interconnect-names = "ufs-ddr", "cpu-ufs"; 140 141 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 142 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 143 <&gcc GCC_UFS_PHY_AHB_CLK>, 144 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 145 <&rpmhcc RPMH_CXO_CLK>, 146 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 147 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 148 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 149 clock-names = "core_clk", 150 "bus_aggr_clk", 151 "iface_clk", 152 "core_clk_unipro", 153 "ref_clk", 154 "tx_lane0_sync_clk", 155 "rx_lane0_sync_clk", 156 "rx_lane1_sync_clk"; 157 freq-table-hz = <75000000 300000000>, 158 <0 0>, 159 <0 0>, 160 <75000000 300000000>, 161 <75000000 300000000>, 162 <0 0>, 163 <0 0>, 164 <0 0>; 165 qcom,ice = <&ice>; 166 }; 167 }; 168