1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) 8 9maintainers: 10 - Alex Elder <elder@kernel.org> 11 12description: 13 The SpacemiT K1 SoC implements a SPI controller that has two 32-entry 14 FIFOs, for transmit and receive. Details are currently available in 15 section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone 16 K1 Documentation[1]. The controller transfers words using PIO. DMA 17 transfers are supported as well, if both TX and RX DMA channels are 18 specified, 19 20 [1] https://developer.spacemit.com/documentation 21 22allOf: 23 - $ref: /schemas/spi/spi-controller.yaml# 24 25properties: 26 compatible: 27 const: spacemit,k1-spi 28 29 reg: 30 maxItems: 1 31 32 clocks: 33 items: 34 - description: Core clock 35 - description: Bus clock 36 37 clock-names: 38 items: 39 - const: core 40 - const: bus 41 42 resets: 43 maxItems: 1 44 45 interrupts: 46 maxItems: 1 47 48 dmas: 49 items: 50 - description: RX DMA channel 51 - description: TX DMA channel 52 53 dma-names: 54 items: 55 - const: rx 56 - const: tx 57 58required: 59 - compatible 60 - reg 61 - clocks 62 - clock-names 63 - resets 64 - interrupts 65 66unevaluatedProperties: false 67 68examples: 69 - | 70 71 #include <dt-bindings/clock/spacemit,k1-syscon.h> 72 spi@d401c000 { 73 compatible = "spacemit,k1-spi"; 74 reg = <0xd401c000 0x30>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 clocks = <&syscon_apbc CLK_SSP3>, 78 <&syscon_apbc CLK_SSP3_BUS>; 79 clock-names = "core", "bus"; 80 resets = <&syscon_apbc RESET_SSP3>; 81 interrupts = <55>; 82 dmas = <&pdma 20>, <&pdma 19>; 83 dma-names = "rx", "tx"; 84 }; 85