1fd6bc2baSMd Sadre Alam# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fd6bc2baSMd Sadre Alam%YAML 1.2 3fd6bc2baSMd Sadre Alam--- 4fd6bc2baSMd Sadre Alam$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# 5fd6bc2baSMd Sadre Alam$schema: http://devicetree.org/meta-schemas/core.yaml# 6fd6bc2baSMd Sadre Alam 7fd6bc2baSMd Sadre Alamtitle: Qualcomm QPIC NAND controller 8fd6bc2baSMd Sadre Alam 9fd6bc2baSMd Sadre Alammaintainers: 10fd6bc2baSMd Sadre Alam - Md sadre Alam <quic_mdalam@quicinc.com> 11fd6bc2baSMd Sadre Alam 12fd6bc2baSMd Sadre Alamdescription: 13fd6bc2baSMd Sadre Alam The QCOM QPIC-SPI-NAND flash controller is an extended version of 14fd6bc2baSMd Sadre Alam the QCOM QPIC NAND flash controller. It can work both in serial 15fd6bc2baSMd Sadre Alam and parallel mode. It supports typical SPI-NAND page cache 16fd6bc2baSMd Sadre Alam operations in single, dual or quad IO mode with pipelined ECC 17fd6bc2baSMd Sadre Alam encoding/decoding using the QPIC ECC HW engine. 18fd6bc2baSMd Sadre Alam 19fd6bc2baSMd Sadre AlamallOf: 20fd6bc2baSMd Sadre Alam - $ref: /schemas/spi/spi-controller.yaml# 21fd6bc2baSMd Sadre Alam 22fd6bc2baSMd Sadre Alamproperties: 23fd6bc2baSMd Sadre Alam compatible: 24*2dbe74c6SGeorge Moussalem oneOf: 25*2dbe74c6SGeorge Moussalem - items: 26*2dbe74c6SGeorge Moussalem - enum: 27*2dbe74c6SGeorge Moussalem - qcom,ipq5018-snand 28*2dbe74c6SGeorge Moussalem - const: qcom,ipq9574-snand 29*2dbe74c6SGeorge Moussalem - const: qcom,ipq9574-snand 30fd6bc2baSMd Sadre Alam 31fd6bc2baSMd Sadre Alam reg: 32fd6bc2baSMd Sadre Alam maxItems: 1 33fd6bc2baSMd Sadre Alam 34fd6bc2baSMd Sadre Alam clocks: 35fd6bc2baSMd Sadre Alam maxItems: 3 36fd6bc2baSMd Sadre Alam 37fd6bc2baSMd Sadre Alam clock-names: 38fd6bc2baSMd Sadre Alam items: 39fd6bc2baSMd Sadre Alam - const: core 40fd6bc2baSMd Sadre Alam - const: aon 41fd6bc2baSMd Sadre Alam - const: iom 42fd6bc2baSMd Sadre Alam 43fd6bc2baSMd Sadre Alam dmas: 44fd6bc2baSMd Sadre Alam items: 45fd6bc2baSMd Sadre Alam - description: tx DMA channel 46fd6bc2baSMd Sadre Alam - description: rx DMA channel 47fd6bc2baSMd Sadre Alam - description: cmd DMA channel 48fd6bc2baSMd Sadre Alam 49fd6bc2baSMd Sadre Alam dma-names: 50fd6bc2baSMd Sadre Alam items: 51fd6bc2baSMd Sadre Alam - const: tx 52fd6bc2baSMd Sadre Alam - const: rx 53fd6bc2baSMd Sadre Alam - const: cmd 54fd6bc2baSMd Sadre Alam 55fd6bc2baSMd Sadre Alamrequired: 56fd6bc2baSMd Sadre Alam - compatible 57fd6bc2baSMd Sadre Alam - reg 58fd6bc2baSMd Sadre Alam - clocks 59fd6bc2baSMd Sadre Alam - clock-names 60fd6bc2baSMd Sadre Alam 61fd6bc2baSMd Sadre AlamunevaluatedProperties: false 62fd6bc2baSMd Sadre Alam 63fd6bc2baSMd Sadre Alamexamples: 64fd6bc2baSMd Sadre Alam - | 65fd6bc2baSMd Sadre Alam #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 66fd6bc2baSMd Sadre Alam spi@79b0000 { 67fd6bc2baSMd Sadre Alam compatible = "qcom,ipq9574-snand"; 68fd6bc2baSMd Sadre Alam reg = <0x1ac00000 0x800>; 69fd6bc2baSMd Sadre Alam 70fd6bc2baSMd Sadre Alam clocks = <&gcc GCC_QPIC_CLK>, 71fd6bc2baSMd Sadre Alam <&gcc GCC_QPIC_AHB_CLK>, 72fd6bc2baSMd Sadre Alam <&gcc GCC_QPIC_IO_MACRO_CLK>; 73fd6bc2baSMd Sadre Alam clock-names = "core", "aon", "iom"; 74fd6bc2baSMd Sadre Alam 75fd6bc2baSMd Sadre Alam #address-cells = <1>; 76fd6bc2baSMd Sadre Alam #size-cells = <0>; 77fd6bc2baSMd Sadre Alam 78fd6bc2baSMd Sadre Alam flash@0 { 79fd6bc2baSMd Sadre Alam compatible = "spi-nand"; 80fd6bc2baSMd Sadre Alam reg = <0>; 81fd6bc2baSMd Sadre Alam #address-cells = <1>; 82fd6bc2baSMd Sadre Alam #size-cells = <1>; 83fd6bc2baSMd Sadre Alam nand-ecc-engine = <&qpic_nand>; 84fd6bc2baSMd Sadre Alam nand-ecc-strength = <4>; 85fd6bc2baSMd Sadre Alam nand-ecc-step-size = <512>; 86fd6bc2baSMd Sadre Alam }; 87fd6bc2baSMd Sadre Alam }; 88