1*1d562ba0STomer Maimon# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*1d562ba0STomer Maimon%YAML 1.2 3*1d562ba0STomer Maimon--- 4*1d562ba0STomer Maimon$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml# 5*1d562ba0STomer Maimon$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1d562ba0STomer Maimon 7*1d562ba0STomer Maimontitle: Nuvoton NPCM Peripheral SPI (PSPI) Controller 8*1d562ba0STomer Maimon 9*1d562ba0STomer Maimonmaintainers: 10*1d562ba0STomer Maimon - Tomer Maimon <tmaimon77@gmail.com> 11*1d562ba0STomer Maimon 12*1d562ba0STomer MaimonallOf: 13*1d562ba0STomer Maimon - $ref: spi-controller.yaml# 14*1d562ba0STomer Maimon 15*1d562ba0STomer Maimondescription: 16*1d562ba0STomer Maimon Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller. 17*1d562ba0STomer Maimon Nuvoton NPCM7xx SOC supports two PSPI channels. 18*1d562ba0STomer Maimon Nuvoton NPCM8xx SOC support one PSPI channel. 19*1d562ba0STomer Maimon 20*1d562ba0STomer Maimonproperties: 21*1d562ba0STomer Maimon compatible: 22*1d562ba0STomer Maimon enum: 23*1d562ba0STomer Maimon - nuvoton,npcm750-pspi # Poleg NPCM7XX 24*1d562ba0STomer Maimon - nuvoton,npcm845-pspi # Arbel NPCM8XX 25*1d562ba0STomer Maimon 26*1d562ba0STomer Maimon reg: 27*1d562ba0STomer Maimon maxItems: 1 28*1d562ba0STomer Maimon 29*1d562ba0STomer Maimon interrupts: 30*1d562ba0STomer Maimon maxItems: 1 31*1d562ba0STomer Maimon 32*1d562ba0STomer Maimon clocks: 33*1d562ba0STomer Maimon maxItems: 1 34*1d562ba0STomer Maimon description: PSPI reference clock. 35*1d562ba0STomer Maimon 36*1d562ba0STomer Maimon clock-names: 37*1d562ba0STomer Maimon items: 38*1d562ba0STomer Maimon - const: clk_apb5 39*1d562ba0STomer Maimon 40*1d562ba0STomer Maimon resets: 41*1d562ba0STomer Maimon maxItems: 1 42*1d562ba0STomer Maimon 43*1d562ba0STomer Maimonrequired: 44*1d562ba0STomer Maimon - compatible 45*1d562ba0STomer Maimon - reg 46*1d562ba0STomer Maimon - interrupts 47*1d562ba0STomer Maimon - clocks 48*1d562ba0STomer Maimon - clock-names 49*1d562ba0STomer Maimon - resets 50*1d562ba0STomer Maimon 51*1d562ba0STomer MaimonunevaluatedProperties: false 52*1d562ba0STomer Maimon 53*1d562ba0STomer Maimonexamples: 54*1d562ba0STomer Maimon - | 55*1d562ba0STomer Maimon #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 56*1d562ba0STomer Maimon #include <dt-bindings/interrupt-controller/arm-gic.h> 57*1d562ba0STomer Maimon #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> 58*1d562ba0STomer Maimon #include "dt-bindings/gpio/gpio.h" 59*1d562ba0STomer Maimon spi0: spi@f0200000 { 60*1d562ba0STomer Maimon compatible = "nuvoton,npcm750-pspi"; 61*1d562ba0STomer Maimon reg = <0xf0200000 0x1000>; 62*1d562ba0STomer Maimon pinctrl-names = "default"; 63*1d562ba0STomer Maimon pinctrl-0 = <&pspi1_pins>; 64*1d562ba0STomer Maimon #address-cells = <1>; 65*1d562ba0STomer Maimon #size-cells = <0>; 66*1d562ba0STomer Maimon interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 67*1d562ba0STomer Maimon clocks = <&clk NPCM7XX_CLK_APB5>; 68*1d562ba0STomer Maimon clock-names = "clk_apb5"; 69*1d562ba0STomer Maimon resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; 70*1d562ba0STomer Maimon cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 71*1d562ba0STomer Maimon }; 72*1d562ba0STomer Maimon 73