xref: /linux/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.yaml (revision fa5ef105618ae9b5aaa51b3f09e41d88d4514207) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Nuvoton NPCM Peripheral SPI (PSPI) Controller
8
9maintainers:
10  - Tomer Maimon <tmaimon77@gmail.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14
15description:
16  Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller.
17  Nuvoton NPCM7xx SOC supports two PSPI channels.
18  Nuvoton NPCM8xx SOC support one PSPI channel.
19
20properties:
21  compatible:
22    enum:
23      - nuvoton,npcm750-pspi # Poleg NPCM7XX
24      - nuvoton,npcm845-pspi # Arbel NPCM8XX
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    maxItems: 1
34    description: PSPI reference clock.
35
36  clock-names:
37    items:
38      - const: clk_apb5
39
40  resets:
41    maxItems: 1
42
43required:
44  - compatible
45  - reg
46  - interrupts
47  - clocks
48  - clock-names
49  - resets
50
51unevaluatedProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
56    #include <dt-bindings/interrupt-controller/arm-gic.h>
57    #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
58    #include "dt-bindings/gpio/gpio.h"
59    spi0: spi@f0200000 {
60        compatible = "nuvoton,npcm750-pspi";
61        reg = <0xf0200000 0x1000>;
62        pinctrl-names = "default";
63        pinctrl-0 = <&pspi1_pins>;
64        #address-cells = <1>;
65        #size-cells = <0>;
66        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
67        clocks = <&clk NPCM7XX_CLK_APB5>;
68        clock-names = "clk_apb5";
69        resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
70        cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
71    };
72
73