1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max98090.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra audio complex with MAX98090 CODEC 8 9maintainers: 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 12 13allOf: 14 - $ref: nvidia,tegra-audio-common.yaml# 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - pattern: '^[a-z0-9]+,tegra-audio-max98090(-[a-z0-9]+)+$' 21 - const: nvidia,tegra-audio-max98090 22 - items: 23 - enum: 24 - nvidia,tegra-audio-max98090-nyan-big 25 - nvidia,tegra-audio-max98090-nyan-blaze 26 - const: nvidia,tegra-audio-max98090-nyan 27 - const: nvidia,tegra-audio-max98090 28 29 nvidia,audio-routing: 30 $ref: /schemas/types.yaml#/definitions/non-unique-string-array 31 description: | 32 A list of the connections between audio components. 33 Each entry is a pair of strings, the first being the connection's sink, 34 the second being the connection's source. Valid names for sources and 35 sinks are the pins (documented in the binding document), 36 and the jacks on the board. 37 minItems: 2 38 items: 39 enum: 40 # Board Connectors 41 - Headphones 42 - Speakers 43 - Mic Jack 44 - Int Mic 45 46 # CODEC Pins 47 - MIC1 48 - MIC2 49 - DMICL 50 - DMICR 51 - IN1 52 - IN2 53 - IN3 54 - IN4 55 - IN5 56 - IN6 57 - IN12 58 - IN34 59 - IN56 60 - HPL 61 - HPR 62 - SPKL 63 - SPKR 64 - RCVL 65 - RCVR 66 - MICBIAS 67 68required: 69 - nvidia,i2s-controller 70 71unevaluatedProperties: false 72 73examples: 74 - | 75 #include <dt-bindings/clock/tegra124-car.h> 76 77 sound { 78 compatible = "nvidia,tegra-audio-max98090-venice2", 79 "nvidia,tegra-audio-max98090"; 80 nvidia,model = "NVIDIA Tegra Venice2"; 81 82 nvidia,audio-routing = 83 "Headphones", "HPR", 84 "Headphones", "HPL", 85 "Speakers", "SPKR", 86 "Speakers", "SPKL", 87 "Mic Jack", "MICBIAS", 88 "IN34", "Mic Jack"; 89 90 nvidia,i2s-controller = <&tegra_i2s1>; 91 nvidia,audio-codec = <&acodec>; 92 93 clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 94 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 95 <&tegra_car TEGRA124_CLK_EXTERN1>; 96 clock-names = "pll_a", "pll_a_out0", "mclk"; 97 }; 98