xref: /linux/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml (revision 9611c0ce215a66770ccbe5c126bf57ba8c31bcad) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Audio Front End PCM controller for MT8196
8
9maintainers:
10  - Darren Ye <darren.ye@mediatek.com>
11
12properties:
13  compatible:
14    const: mediatek,mt8196-afe
15
16  reg:
17    maxItems: 1
18
19  interrupts:
20    maxItems: 1
21
22  memory-region:
23    maxItems: 1
24
25  power-domains:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: mux for audio intbus
31      - description: mux for audio engen1
32      - description: mux for audio engen2
33      - description: mux for audio h
34      - description: audio apll1 clock
35      - description: audio apll2 clock
36      - description: audio apll12 divide for i2sin0
37      - description: audio apll12 divide for i2sin1
38      - description: audio apll12 divide for fmi2s
39      - description: audio apll12 divide for tdmout mck
40      - description: audio apll12 divide for tdmout bck
41      - description: mux for adsp clock
42
43  clock-names:
44    items:
45      - const: top_aud_intbus
46      - const: top_aud_eng1
47      - const: top_aud_eng2
48      - const: top_aud_h
49      - const: apll1
50      - const: apll2
51      - const: apll12_div_i2sin0
52      - const: apll12_div_i2sin1
53      - const: apll12_div_fmi2s
54      - const: apll12_div_tdmout_m
55      - const: apll12_div_tdmout_b
56      - const: top_adsp
57
58required:
59  - compatible
60  - reg
61  - interrupts
62  - memory-region
63  - power-domains
64  - clocks
65  - clock-names
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/interrupt-controller/irq.h>
73
74    soc {
75        #address-cells = <2>;
76        #size-cells = <2>;
77
78        afe@1a110000 {
79            compatible = "mediatek,mt8196-afe";
80            reg = <0 0x1a110000 0 0x9000>;
81            interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>;
82            memory-region = <&afe_dma_mem_reserved>;
83            power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO
84            pinctrl-names = "default";
85            pinctrl-0 = <&aud_pins_default>;
86            clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL
87                     <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL
88                     <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL
89                     <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL
90                     <&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1
91                     <&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2
92                     <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0
93                     <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1
94                     <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S
95                     <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M
96                     <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B
97                     <&cksys_clk 45>; //CLK_CK_ADSP_SEL
98            clock-names = "top_aud_intbus",
99                          "top_aud_eng1",
100                          "top_aud_eng2",
101                          "top_aud_h",
102                          "apll1",
103                          "apll2",
104                          "apll12_div_i2sin0",
105                          "apll12_div_i2sin1",
106                          "apll12_div_fmi2s",
107                          "apll12_div_tdmout_m",
108                          "apll12_div_tdmout_b",
109                          "top_adsp";
110        };
111    };
112
113...
114