xref: /linux/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung's Exynos USI (Universal Serial Interface)
8
9maintainers:
10  - Sam Protsenko <semen.protsenko@linaro.org>
11  - Krzysztof Kozlowski <krzk@kernel.org>
12
13description: |
14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15  USI shares almost all internal circuits within each protocol, so only one
16  protocol can be chosen at a time. USI is modeled as a node with zero or more
17  child nodes, each representing a serial sub-node device. The mode setting
18  selects which particular function will be used.
19
20properties:
21  $nodename:
22    pattern: "^usi@[0-9a-f]+$"
23
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - google,gs101-usi
29              - samsung,exynosautov9-usi
30              - samsung,exynosautov920-usi
31          - const: samsung,exynos850-usi
32      - enum:
33          - samsung,exynos850-usi
34
35  reg: true
36
37  clocks: true
38
39  clock-names: true
40
41  ranges: true
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  samsung,sysreg:
50    $ref: /schemas/types.yaml#/definitions/phandle-array
51    items:
52      - items:
53          - description: phandle to System Register syscon node
54          - description: offset of SW_CONF register for this USI controller
55    description:
56      Should be phandle/offset pair. The phandle to System Register syscon node
57      (for the same domain where this USI controller resides) and the offset
58      of SW_CONF register for this USI controller.
59
60  samsung,mode:
61    $ref: /schemas/types.yaml#/definitions/uint32
62    description:
63      Selects USI function (which serial protocol to use). Refer to
64      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
65
66  samsung,clkreq-on:
67    type: boolean
68    description:
69      Enable this property if underlying protocol requires the clock to be
70      continuously provided without automatic gating. As suggested by SoC
71      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
72      multi-master mode. Usually this property is needed if USI mode is set
73      to "UART".
74
75      This property is optional.
76
77patternProperties:
78  "^i2c@[0-9a-f]+$":
79    $ref: /schemas/i2c/i2c-exynos5.yaml
80    description: Child node describing underlying I2C
81
82  "^serial@[0-9a-f]+$":
83    $ref: /schemas/serial/samsung_uart.yaml
84    description: Child node describing underlying UART/serial
85
86  "^spi@[0-9a-f]+$":
87    $ref: /schemas/spi/samsung,spi.yaml
88    description: Child node describing underlying SPI
89
90required:
91  - compatible
92  - ranges
93  - "#address-cells"
94  - "#size-cells"
95  - samsung,sysreg
96  - samsung,mode
97
98if:
99  properties:
100    compatible:
101      contains:
102        enum:
103          - samsung,exynos850-usi
104
105then:
106  properties:
107    reg:
108      maxItems: 1
109
110    clocks:
111      items:
112        - description: Bus (APB) clock
113        - description: Operating clock for UART/SPI/I2C protocol
114
115    clock-names:
116      items:
117        - const: pclk
118        - const: ipclk
119
120  required:
121    - reg
122    - clocks
123    - clock-names
124
125else:
126  properties:
127    reg: false
128    clocks: false
129    clock-names: false
130    samsung,clkreq-on: false
131
132additionalProperties: false
133
134examples:
135  - |
136    #include <dt-bindings/interrupt-controller/arm-gic.h>
137    #include <dt-bindings/soc/samsung,exynos-usi.h>
138
139    usi0: usi@138200c0 {
140        compatible = "samsung,exynos850-usi";
141        reg = <0x138200c0 0x20>;
142        samsung,sysreg = <&sysreg_peri 0x1010>;
143        samsung,mode = <USI_V2_UART>;
144        samsung,clkreq-on; /* needed for UART mode */
145        #address-cells = <1>;
146        #size-cells = <1>;
147        ranges;
148        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
149        clock-names = "pclk", "ipclk";
150
151        serial_0: serial@13820000 {
152            compatible = "samsung,exynos850-uart";
153            reg = <0x13820000 0xc0>;
154            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
155            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
156            clock-names = "uart", "clk_uart_baud0";
157            status = "disabled";
158        };
159
160        hsi2c_0: i2c@13820000 {
161            compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
162            reg = <0x13820000 0xc0>;
163            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
164            #address-cells = <1>;
165            #size-cells = <0>;
166            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
167            clock-names = "hsi2c", "hsi2c_pclk";
168            status = "disabled";
169        };
170    };
171