xref: /linux/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml (revision 7a5e832d05025a3679d0fcd60584e6e946a3e358) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung's Exynos USI (Universal Serial Interface)
8
9maintainers:
10  - Sam Protsenko <semen.protsenko@linaro.org>
11  - Krzysztof Kozlowski <krzk@kernel.org>
12
13description: |
14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15  USI shares almost all internal circuits within each protocol, so only one
16  protocol can be chosen at a time. USI is modeled as a node with zero or more
17  child nodes, each representing a serial sub-node device. The mode setting
18  selects which particular function will be used.
19
20properties:
21  $nodename:
22    pattern: "^usi@[0-9a-f]+$"
23
24  compatible:
25    oneOf:
26      - items:
27          - enum:
28              - samsung,exynosautov9-usi
29              - samsung,exynosautov920-usi
30          - const: samsung,exynos850-usi
31      - enum:
32          - samsung,exynos850-usi
33
34  reg: true
35
36  clocks: true
37
38  clock-names: true
39
40  ranges: true
41
42  "#address-cells":
43    const: 1
44
45  "#size-cells":
46    const: 1
47
48  samsung,sysreg:
49    $ref: /schemas/types.yaml#/definitions/phandle-array
50    items:
51      - items:
52          - description: phandle to System Register syscon node
53          - description: offset of SW_CONF register for this USI controller
54    description:
55      Should be phandle/offset pair. The phandle to System Register syscon node
56      (for the same domain where this USI controller resides) and the offset
57      of SW_CONF register for this USI controller.
58
59  samsung,mode:
60    $ref: /schemas/types.yaml#/definitions/uint32
61    description:
62      Selects USI function (which serial protocol to use). Refer to
63      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
64
65  samsung,clkreq-on:
66    type: boolean
67    description:
68      Enable this property if underlying protocol requires the clock to be
69      continuously provided without automatic gating. As suggested by SoC
70      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
71      multi-master mode. Usually this property is needed if USI mode is set
72      to "UART".
73
74      This property is optional.
75
76patternProperties:
77  "^i2c@[0-9a-f]+$":
78    $ref: /schemas/i2c/i2c-exynos5.yaml
79    description: Child node describing underlying I2C
80
81  "^serial@[0-9a-f]+$":
82    $ref: /schemas/serial/samsung_uart.yaml
83    description: Child node describing underlying UART/serial
84
85  "^spi@[0-9a-f]+$":
86    $ref: /schemas/spi/samsung,spi.yaml
87    description: Child node describing underlying SPI
88
89required:
90  - compatible
91  - ranges
92  - "#address-cells"
93  - "#size-cells"
94  - samsung,sysreg
95  - samsung,mode
96
97if:
98  properties:
99    compatible:
100      contains:
101        enum:
102          - samsung,exynos850-usi
103
104then:
105  properties:
106    reg:
107      maxItems: 1
108
109    clocks:
110      items:
111        - description: Bus (APB) clock
112        - description: Operating clock for UART/SPI/I2C protocol
113
114    clock-names:
115      items:
116        - const: pclk
117        - const: ipclk
118
119  required:
120    - reg
121    - clocks
122    - clock-names
123
124else:
125  properties:
126    reg: false
127    clocks: false
128    clock-names: false
129    samsung,clkreq-on: false
130
131additionalProperties: false
132
133examples:
134  - |
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136    #include <dt-bindings/soc/samsung,exynos-usi.h>
137
138    usi0: usi@138200c0 {
139        compatible = "samsung,exynos850-usi";
140        reg = <0x138200c0 0x20>;
141        samsung,sysreg = <&sysreg_peri 0x1010>;
142        samsung,mode = <USI_V2_UART>;
143        samsung,clkreq-on; /* needed for UART mode */
144        #address-cells = <1>;
145        #size-cells = <1>;
146        ranges;
147        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
148        clock-names = "pclk", "ipclk";
149
150        serial_0: serial@13820000 {
151            compatible = "samsung,exynos850-uart";
152            reg = <0x13820000 0xc0>;
153            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
154            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
155            clock-names = "uart", "clk_uart_baud0";
156            status = "disabled";
157        };
158
159        hsi2c_0: i2c@13820000 {
160            compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
161            reg = <0x13820000 0xc0>;
162            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
163            #address-cells = <1>;
164            #size-cells = <0>;
165            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
166            clock-names = "hsi2c", "hsi2c_pclk";
167            status = "disabled";
168        };
169    };
170