xref: /linux/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml (revision 31b43c079f9aa55754c20404a42bca9a49e01f60) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-irqmux.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Polarfire SoC GPIO Interrupt Mux
8
9maintainers:
10  - Conor Dooley <conor.dooley@microchip.com>
11
12description: |
13  There are 3 GPIO controllers on this SoC, of which:
14  - GPIO controller 0 has 14 GPIOs
15  - GPIO controller 1 has 24 GPIOs
16  - GPIO controller 2 has 32 GPIOs
17
18  All GPIOs are capable of generating interrupts, for a total of 70.
19  There are only 41 IRQs available however, so a configurable mux is used to
20  ensure all GPIOs can be used for interrupt generation.
21  38 of the 41 interrupts are in what the documentation calls "direct mode",
22  as they provide an exclusive connection from a GPIO to the PLIC.
23  Lines 18 to 23 on GPIO controller 1 are always in "direct mode".
24  The 3 remaining interrupts are used to mux the interrupts which do not have
25  a exclusive connection, one for each GPIO controller.
26
27properties:
28  compatible:
29    const: microchip,mpfs-irqmux
30
31  reg:
32    maxItems: 1
33
34  "#address-cells":
35    const: 0
36
37  "#interrupt-cells":
38    const: 1
39
40  interrupt-map-mask:
41    items:
42      - const: 0x7f
43
44  interrupt-map:
45    description: |
46      Specifies the mapping from GPIO interrupt lines to plic interrupts.
47
48      The child interrupt number set in arrays items is computed using the
49      following formula:
50          gpio_bank * 32 + gpio_number
51      with:
52        - gpio_bank: The GPIO bank number
53            - 0 for GPIO0,
54            - 1 for GPIO1,
55            - 2 for GPIO2
56        - gpio_number: Number of the gpio in the bank (0..31)
57    maxItems: 70
58
59required:
60  - compatible
61  - reg
62  - "#address-cells"
63  - "#interrupt-cells"
64  - interrupt-map-mask
65  - interrupt-map
66
67additionalProperties: false
68
69examples:
70  - |
71    interrupt-controller@54 {
72        compatible = "microchip,mpfs-irqmux";
73        reg = <0x54 0x4>;
74        #address-cells = <0>;
75        #interrupt-cells = <1>;
76        interrupt-map-mask = <0x7f>;
77        interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
78                        <3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
79                        <6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
80                        <9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
81                        <12 &plic 25>, <13 &plic 26>,
82
83                        <32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
84                        <35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
85                        <38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
86                        <41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
87                        <44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
88                        <47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
89                        <50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
90                        <53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
91
92                        <64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
93                        <67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
94                        <70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
95                        <73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
96                        <76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
97                        <79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
98                        <82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
99                        <85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
100                        <88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
101                        <91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
102                        <94 &plic 53>, <95 &plic 53>;
103    };
104