xref: /linux/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cix Sky1 audio subsystem clock and reset unit
8
9maintainers:
10  - Joakim Zhang <joakim.zhang@cixtech.com>
11
12description: |
13  The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups
14  audio-related clock muxing, gating and block-level software reset control
15  in a single register block.
16
17  A single device node exposes both the clock controller and software reset
18  lines. The clock driver registers as a platform driver; the reset controller
19  is registered by an auxiliary driver bound from the clock driver.
20
21  Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS
22  clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are
23  defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.
24
25  Block-level software reset indices are exposed via #reset-cells; indices
26  are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.
27
28  The SoC syscon NoC (or bus) reset is described via resets. The audio
29  subsystem power domain is described via power-domains.
30
31properties:
32  compatible:
33    const: cix,sky1-audss-cru
34
35  reg:
36    maxItems: 1
37
38  '#clock-cells':
39    const: 1
40    description:
41      Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.
42
43  '#reset-cells':
44    const: 1
45    description:
46      Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.
47
48  clocks:
49    items:
50      - description: I2S parent clock for sampling rates multiple of 8kHz.
51      - description: I2S parent clock for sampling rates multiple of 11.025kHz.
52      - description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox).
53      - description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock.
54
55  clock-names:
56    items:
57      - const: x8k
58      - const: x11k
59      - const: sys
60      - const: 48m
61
62  power-domains:
63    maxItems: 1
64
65  resets:
66    maxItems: 1
67
68required:
69  - compatible
70  - reg
71  - '#clock-cells'
72  - '#reset-cells'
73  - clocks
74  - clock-names
75  - power-domains
76  - resets
77
78additionalProperties: false
79
80examples:
81  - |
82    audss_cru: clock-controller@7110000 {
83        compatible = "cix,sky1-audss-cru";
84        reg = <0x7110000 0x10000>;
85        #clock-cells = <1>;
86        #reset-cells = <1>;
87        clocks = <&scmi_clk 76>, <&scmi_clk 78>,
88                 <&scmi_clk 70>, <&scmi_clk 71>;
89        clock-names = "x8k", "x11k", "sys", "48m";
90        power-domains = <&smc_devpd 0>;
91        resets = <&s5_syscon 31>;
92    };
93