1*25ef9563SFrank Li# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*25ef9563SFrank Li%YAML 1.2 3*25ef9563SFrank Li--- 4*25ef9563SFrank Li$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml# 5*25ef9563SFrank Li$schema: http://devicetree.org/meta-schemas/core.yaml# 6*25ef9563SFrank Li 7*25ef9563SFrank Lititle: NXP LPC1850 Reset Generation Unit (RGU) 8*25ef9563SFrank Li 9*25ef9563SFrank Limaintainers: 10*25ef9563SFrank Li - Frank Li <Frank.Li@nxp.com> 11*25ef9563SFrank Li 12*25ef9563SFrank Liproperties: 13*25ef9563SFrank Li compatible: 14*25ef9563SFrank Li const: nxp,lpc1850-rgu 15*25ef9563SFrank Li 16*25ef9563SFrank Li reg: 17*25ef9563SFrank Li maxItems: 1 18*25ef9563SFrank Li 19*25ef9563SFrank Li clocks: 20*25ef9563SFrank Li maxItems: 2 21*25ef9563SFrank Li 22*25ef9563SFrank Li clock-names: 23*25ef9563SFrank Li items: 24*25ef9563SFrank Li - const: delay 25*25ef9563SFrank Li - const: reg 26*25ef9563SFrank Li 27*25ef9563SFrank Li '#reset-cells': 28*25ef9563SFrank Li const: 1 29*25ef9563SFrank Li description: | 30*25ef9563SFrank Li See table below for valid peripheral reset numbers. Numbers not 31*25ef9563SFrank Li in the table below are either reserved or not applicable for 32*25ef9563SFrank Li normal operation. 33*25ef9563SFrank Li 34*25ef9563SFrank Li Reset Peripheral 35*25ef9563SFrank Li 9 System control unit (SCU) 36*25ef9563SFrank Li 12 ARM Cortex-M0 subsystem core (LPC43xx only) 37*25ef9563SFrank Li 13 CPU core 38*25ef9563SFrank Li 16 LCD controller 39*25ef9563SFrank Li 17 USB0 40*25ef9563SFrank Li 18 USB1 41*25ef9563SFrank Li 19 DMA 42*25ef9563SFrank Li 20 SDIO 43*25ef9563SFrank Li 21 External memory controller (EMC) 44*25ef9563SFrank Li 22 Ethernet 45*25ef9563SFrank Li 25 Flash bank A 46*25ef9563SFrank Li 27 EEPROM 47*25ef9563SFrank Li 28 GPIO 48*25ef9563SFrank Li 29 Flash bank B 49*25ef9563SFrank Li 32 Timer0 50*25ef9563SFrank Li 33 Timer1 51*25ef9563SFrank Li 34 Timer2 52*25ef9563SFrank Li 35 Timer3 53*25ef9563SFrank Li 36 Repetitive Interrupt timer (RIT) 54*25ef9563SFrank Li 37 State Configurable Timer (SCT) 55*25ef9563SFrank Li 38 Motor control PWM (MCPWM) 56*25ef9563SFrank Li 39 QEI 57*25ef9563SFrank Li 40 ADC0 58*25ef9563SFrank Li 41 ADC1 59*25ef9563SFrank Li 42 DAC 60*25ef9563SFrank Li 44 USART0 61*25ef9563SFrank Li 45 UART1 62*25ef9563SFrank Li 46 USART2 63*25ef9563SFrank Li 47 USART3 64*25ef9563SFrank Li 48 I2C0 65*25ef9563SFrank Li 49 I2C1 66*25ef9563SFrank Li 50 SSP0 67*25ef9563SFrank Li 51 SSP1 68*25ef9563SFrank Li 52 I2S0 and I2S1 69*25ef9563SFrank Li 53 Serial Flash Interface (SPIFI) 70*25ef9563SFrank Li 54 C_CAN1 71*25ef9563SFrank Li 55 C_CAN0 72*25ef9563SFrank Li 56 ARM Cortex-M0 application core (LPC4370 only) 73*25ef9563SFrank Li 57 SGPIO (LPC43xx only) 74*25ef9563SFrank Li 58 SPI (LPC43xx only) 75*25ef9563SFrank Li 60 ADCHS (12-bit ADC) (LPC4370 only) 76*25ef9563SFrank Li 77*25ef9563SFrank Li Refer to NXP LPC18xx or LPC43xx user manual for more details about 78*25ef9563SFrank Li the reset signals and the connected block/peripheral. 79*25ef9563SFrank Li 80*25ef9563SFrank Lirequired: 81*25ef9563SFrank Li - compatible 82*25ef9563SFrank Li - reg 83*25ef9563SFrank Li - clocks 84*25ef9563SFrank Li - clock-names 85*25ef9563SFrank Li - '#reset-cells' 86*25ef9563SFrank Li 87*25ef9563SFrank LiadditionalProperties: false 88*25ef9563SFrank Li 89*25ef9563SFrank Liexamples: 90*25ef9563SFrank Li - | 91*25ef9563SFrank Li #include <dt-bindings/clock/lpc18xx-ccu.h> 92*25ef9563SFrank Li #include <dt-bindings/clock/lpc18xx-cgu.h> 93*25ef9563SFrank Li 94*25ef9563SFrank Li reset-controller@40053000 { 95*25ef9563SFrank Li compatible = "nxp,lpc1850-rgu"; 96*25ef9563SFrank Li reg = <0x40053000 0x1000>; 97*25ef9563SFrank Li clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 98*25ef9563SFrank Li clock-names = "delay", "reg"; 99*25ef9563SFrank Li #reset-cells = <1>; 100*25ef9563SFrank Li }; 101*25ef9563SFrank Li 102