xref: /linux/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.yaml (revision 0f46f50845ce75bfaba62df0421084d23bb6a72f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP LPC1850  Reset Generation Unit (RGU)
8
9maintainers:
10  - Frank Li <Frank.Li@nxp.com>
11
12properties:
13  compatible:
14    const: nxp,lpc1850-rgu
15
16  reg:
17    maxItems: 1
18
19  clocks:
20    maxItems: 2
21
22  clock-names:
23    items:
24      - const: delay
25      - const: reg
26
27  '#reset-cells':
28    const: 1
29    description: |
30      See table below for valid peripheral reset numbers. Numbers not
31      in the table below are either reserved or not applicable for
32      normal operation.
33
34      Reset	Peripheral
35        9	System control unit (SCU)
36       12	ARM Cortex-M0 subsystem core (LPC43xx only)
37       13	CPU core
38       16	LCD controller
39       17	USB0
40       18	USB1
41       19	DMA
42       20	SDIO
43       21	External memory controller (EMC)
44       22	Ethernet
45       25	Flash bank A
46       27	EEPROM
47       28	GPIO
48       29	Flash bank B
49       32	Timer0
50       33	Timer1
51       34	Timer2
52       35	Timer3
53       36	Repetitive Interrupt timer (RIT)
54       37	State Configurable Timer (SCT)
55       38	Motor control PWM (MCPWM)
56       39	QEI
57       40	ADC0
58       41	ADC1
59       42	DAC
60       44	USART0
61       45	UART1
62       46	USART2
63       47	USART3
64       48	I2C0
65       49	I2C1
66       50	SSP0
67       51	SSP1
68       52	I2S0 and I2S1
69       53	Serial Flash Interface (SPIFI)
70       54	C_CAN1
71       55	C_CAN0
72       56	ARM Cortex-M0 application core (LPC4370 only)
73       57	SGPIO (LPC43xx only)
74       58	SPI (LPC43xx only)
75       60	ADCHS (12-bit ADC) (LPC4370 only)
76
77      Refer to NXP LPC18xx or LPC43xx user manual for more details about
78      the reset signals and the connected block/peripheral.
79
80required:
81  - compatible
82  - reg
83  - clocks
84  - clock-names
85  - '#reset-cells'
86
87additionalProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/clock/lpc18xx-ccu.h>
92    #include <dt-bindings/clock/lpc18xx-cgu.h>
93
94    reset-controller@40053000 {
95        compatible = "nxp,lpc1850-rgu";
96        reg = <0x40053000 0x1000>;
97        clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
98        clock-names = "delay", "reg";
99        #reset-cells = <1>;
100    };
101
102