1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx R5F processor subsystem 8 9maintainers: 10 - Ben Levinsky <ben.levinsky@amd.com> 11 - Tanmay Shah <tanmay.shah@amd.com> 12 13description: | 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. 18 19properties: 20 compatible: 21 enum: 22 - xlnx,zynqmp-r5fss 23 - xlnx,versal-r5fss 24 - xlnx,versal-net-r52fss 25 26 "#address-cells": 27 const: 2 28 29 "#size-cells": 30 const: 2 31 32 ranges: 33 description: | 34 Standard ranges definition providing address translations for 35 local R5F TCM address spaces to bus addresses. 36 37 xlnx,cluster-mode: 38 $ref: /schemas/types.yaml#/definitions/uint32 39 enum: [0, 1, 2] 40 default: 1 41 description: | 42 The RPU MPCore can operate in split mode (Dual-processor performance), Safety 43 lock-step mode(Both RPU cores execute the same code in lock-step, 44 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while 45 core 1 runs normally). The processor does not support dynamic configuration. 46 Switching between modes is only permitted immediately after a processor reset. 47 If set to 1 then lockstep mode and if 0 then split mode. 48 If set to 2 then single CPU mode. When not defined, default will be lockstep mode. 49 In summary, 50 0: split mode 51 1: lockstep mode (default) 52 2: single cpu mode 53 54 xlnx,tcm-mode: 55 $ref: /schemas/types.yaml#/definitions/uint32 56 enum: [0, 1] 57 description: | 58 Configure RPU TCM 59 0: split mode 60 1: lockstep mode 61 62patternProperties: 63 "^r(.*)@[0-9a-f]+$": 64 type: object 65 description: | 66 The RPU is located in the Low Power Domain of the Processor Subsystem. 67 Each processor includes separate L1 instruction and data caches and 68 tightly coupled memories (TCM). System memory is cacheable, but the TCM 69 memory space is non-cacheable. 70 71 Each RPU contains one 64KB memory and two 32KB memories that 72 are accessed via the TCM A and B port interfaces, for a total of 128KB 73 per processor. In lock-step mode, the processor has access to 256KB of 74 TCM memory. 75 76 properties: 77 compatible: 78 enum: 79 - xlnx,zynqmp-r5f 80 - xlnx,versal-r5f 81 - xlnx,versal-net-r52f 82 83 reg: 84 minItems: 1 85 maxItems: 4 86 87 reg-names: 88 minItems: 1 89 maxItems: 4 90 91 power-domains: 92 minItems: 2 93 maxItems: 5 94 95 mboxes: 96 minItems: 1 97 items: 98 - description: mailbox channel to send data to RPU 99 - description: mailbox channel to receive data from RPU 100 101 mbox-names: 102 minItems: 1 103 items: 104 - const: tx 105 - const: rx 106 107 sram: 108 $ref: /schemas/types.yaml#/definitions/phandle-array 109 minItems: 1 110 maxItems: 8 111 items: 112 maxItems: 1 113 description: | 114 phandles to one or more reserved on-chip SRAM regions. Other than TCM, 115 the RPU can execute instructions and access data from the OCM memory, 116 the main DDR memory, and other system memories. 117 118 The regions should be defined as child nodes of the respective SRAM 119 node, and should be defined as per the generic bindings in 120 Documentation/devicetree/bindings/sram/sram.yaml 121 122 memory-region: 123 description: | 124 List of phandles to the reserved memory regions associated with the 125 remoteproc device. This is variable and describes the memories shared with 126 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg 127 vrings, ...). This reserved memory region will be allocated in DDR memory. 128 minItems: 1 129 maxItems: 8 130 items: 131 - description: region used for RPU firmware image section 132 - description: vdev buffer 133 - description: vring0 134 - description: vring1 135 additionalItems: true 136 137 required: 138 - compatible 139 - reg 140 - reg-names 141 - power-domains 142 143required: 144 - compatible 145 - "#address-cells" 146 - "#size-cells" 147 - ranges 148 149allOf: 150 - if: 151 properties: 152 compatible: 153 contains: 154 enum: 155 - xlnx,versal-net-r52fss 156 then: 157 properties: 158 xlnx,tcm-mode: false 159 160 patternProperties: 161 "^r52f@[0-9a-f]+$": 162 type: object 163 164 properties: 165 reg: 166 minItems: 1 167 items: 168 - description: ATCM internal memory 169 - description: BTCM internal memory 170 - description: CTCM internal memory 171 172 reg-names: 173 minItems: 1 174 items: 175 - const: atcm0 176 - const: btcm0 177 - const: ctcm0 178 179 power-domains: 180 minItems: 2 181 items: 182 - description: RPU core power domain 183 - description: ATCM power domain 184 - description: BTCM power domain 185 - description: CTCM power domain 186 187 - if: 188 properties: 189 compatible: 190 contains: 191 enum: 192 - xlnx,zynqmp-r5fss 193 - xlnx,versal-r5fss 194 then: 195 if: 196 properties: 197 xlnx,cluster-mode: 198 enum: [1, 2] 199 then: 200 properties: 201 xlnx,tcm-mode: 202 enum: [1] 203 204 patternProperties: 205 "^r5f@[0-9a-f]+$": 206 type: object 207 208 properties: 209 reg: 210 minItems: 1 211 items: 212 - description: ATCM internal memory 213 - description: BTCM internal memory 214 - description: extra ATCM memory in lockstep mode 215 - description: extra BTCM memory in lockstep mode 216 217 reg-names: 218 minItems: 1 219 items: 220 - const: atcm0 221 - const: btcm0 222 - const: atcm1 223 - const: btcm1 224 225 power-domains: 226 minItems: 2 227 items: 228 - description: RPU core power domain 229 - description: ATCM power domain 230 - description: BTCM power domain 231 - description: second ATCM power domain 232 - description: second BTCM power domain 233 234 required: 235 - xlnx,tcm-mode 236 237 else: 238 properties: 239 xlnx,tcm-mode: 240 enum: [0] 241 242 patternProperties: 243 "^r5f@[0-9a-f]+$": 244 type: object 245 246 properties: 247 reg: 248 minItems: 1 249 items: 250 - description: ATCM internal memory 251 - description: BTCM internal memory 252 253 reg-names: 254 minItems: 1 255 items: 256 - const: atcm0 257 - const: btcm0 258 259 power-domains: 260 minItems: 2 261 items: 262 - description: RPU core power domain 263 - description: ATCM power domain 264 - description: BTCM power domain 265 266 required: 267 - xlnx,tcm-mode 268 269additionalProperties: false 270 271examples: 272 - | 273 #include <dt-bindings/power/xlnx-zynqmp-power.h> 274 275 // Split mode configuration 276 soc { 277 #address-cells = <2>; 278 #size-cells = <2>; 279 280 remoteproc@ffe00000 { 281 compatible = "xlnx,zynqmp-r5fss"; 282 xlnx,cluster-mode = <0>; 283 xlnx,tcm-mode = <0>; 284 285 #address-cells = <2>; 286 #size-cells = <2>; 287 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 288 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 289 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, 290 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; 291 292 r5f@0 { 293 compatible = "xlnx,zynqmp-r5f"; 294 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; 295 reg-names = "atcm0", "btcm0"; 296 power-domains = <&zynqmp_firmware PD_RPU_0>, 297 <&zynqmp_firmware PD_R5_0_ATCM>, 298 <&zynqmp_firmware PD_R5_0_BTCM>; 299 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, 300 <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; 301 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; 302 mbox-names = "tx", "rx"; 303 }; 304 305 r5f@1 { 306 compatible = "xlnx,zynqmp-r5f"; 307 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 308 reg-names = "atcm0", "btcm0"; 309 power-domains = <&zynqmp_firmware PD_RPU_1>, 310 <&zynqmp_firmware PD_R5_1_ATCM>, 311 <&zynqmp_firmware PD_R5_1_BTCM>; 312 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, 313 <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; 314 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; 315 mbox-names = "tx", "rx"; 316 }; 317 }; 318 }; 319 320 - | 321 //Lockstep configuration 322 soc { 323 #address-cells = <2>; 324 #size-cells = <2>; 325 326 remoteproc@ffe00000 { 327 compatible = "xlnx,zynqmp-r5fss"; 328 xlnx,cluster-mode = <1>; 329 xlnx,tcm-mode = <1>; 330 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, 334 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, 335 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, 336 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; 337 338 r5f@0 { 339 compatible = "xlnx,zynqmp-r5f"; 340 reg = <0x0 0x0 0x0 0x10000>, 341 <0x0 0x20000 0x0 0x10000>, 342 <0x0 0x10000 0x0 0x10000>, 343 <0x0 0x30000 0x0 0x10000>; 344 reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; 345 power-domains = <&zynqmp_firmware PD_RPU_0>, 346 <&zynqmp_firmware PD_R5_0_ATCM>, 347 <&zynqmp_firmware PD_R5_0_BTCM>, 348 <&zynqmp_firmware PD_R5_1_ATCM>, 349 <&zynqmp_firmware PD_R5_1_BTCM>; 350 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, 351 <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; 352 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; 353 mbox-names = "tx", "rx"; 354 }; 355 356 r5f@1 { 357 compatible = "xlnx,zynqmp-r5f"; 358 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; 359 reg-names = "atcm0", "btcm0"; 360 power-domains = <&zynqmp_firmware PD_RPU_1>, 361 <&zynqmp_firmware PD_R5_1_ATCM>, 362 <&zynqmp_firmware PD_R5_1_BTCM>; 363 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, 364 <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; 365 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; 366 mbox-names = "tx", "rx"; 367 }; 368 }; 369 }; 370... 371