1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QCS404 CDSP Peripheral Image Loader 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: 13 This document defines the binding for a component that loads and boots firmware 14 on the Qualcomm Technology Inc. CDSP (Compute DSP). 15 16properties: 17 compatible: 18 enum: 19 - qcom,qcs404-cdsp-pil 20 21 reg: 22 maxItems: 1 23 description: 24 The base address and size of the qdsp6ss register 25 26 interrupts: 27 items: 28 - description: Watchdog interrupt 29 - description: Fatal interrupt 30 - description: Ready interrupt 31 - description: Handover interrupt 32 - description: Stop acknowledge interrupt 33 34 interrupt-names: 35 items: 36 - const: wdog 37 - const: fatal 38 - const: ready 39 - const: handover 40 - const: stop-ack 41 42 clocks: 43 items: 44 - description: XO clock 45 - description: SWAY clock 46 - description: TBU clock 47 - description: BIMC clock 48 - description: AHB AON clock 49 - description: Q6SS SLAVE clock 50 - description: Q6SS MASTER clock 51 - description: Q6 AXIM clock 52 53 clock-names: 54 items: 55 - const: xo 56 - const: sway 57 - const: tbu 58 - const: bimc 59 - const: ahb_aon 60 - const: q6ss_slave 61 - const: q6ss_master 62 - const: q6_axim 63 64 power-domains: 65 items: 66 - description: CX power domain 67 68 resets: 69 items: 70 - description: AOSS restart 71 72 reset-names: 73 items: 74 - const: restart 75 76 memory-region: 77 maxItems: 1 78 description: Reference to the reserved-memory for the Hexagon core 79 80 qcom,halt-regs: 81 $ref: /schemas/types.yaml#/definitions/phandle-array 82 description: 83 Phandle reference to a syscon representing TCSR followed by the 84 offset within syscon for q6 halt register. 85 items: 86 - items: 87 - description: phandle to TCSR syscon region 88 - description: offset to the Q6 halt register 89 90 qcom,smem-states: 91 $ref: /schemas/types.yaml#/definitions/phandle-array 92 description: States used by the AP to signal the Hexagon core 93 items: 94 - description: Stop the modem 95 96 qcom,smem-state-names: 97 description: The names of the state bits used for SMP2P output 98 items: 99 - const: stop 100 101required: 102 - compatible 103 - reg 104 - interrupts 105 - interrupt-names 106 - clocks 107 - clock-names 108 - power-domains 109 - resets 110 - reset-names 111 - qcom,halt-regs 112 - memory-region 113 - qcom,smem-states 114 - qcom,smem-state-names 115 116additionalProperties: false 117 118examples: 119 - | 120 #include <dt-bindings/interrupt-controller/arm-gic.h> 121 #include <dt-bindings/clock/qcom,gcc-qcs404.h> 122 #include <dt-bindings/power/qcom-rpmpd.h> 123 #include <dt-bindings/clock/qcom,turingcc-qcs404.h> 124 remoteproc@b00000 { 125 compatible = "qcom,qcs404-cdsp-pil"; 126 reg = <0x00b00000 0x4040>; 127 128 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 129 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 130 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 131 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 132 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 133 interrupt-names = "wdog", "fatal", "ready", 134 "handover", "stop-ack"; 135 136 clocks = <&xo_board>, 137 <&gcc GCC_CDSP_CFG_AHB_CLK>, 138 <&gcc GCC_CDSP_TBU_CLK>, 139 <&gcc GCC_BIMC_CDSP_CLK>, 140 <&turingcc TURING_WRAPPER_AON_CLK>, 141 <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 142 <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 143 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 144 clock-names = "xo", 145 "sway", 146 "tbu", 147 "bimc", 148 "ahb_aon", 149 "q6ss_slave", 150 "q6ss_master", 151 "q6_axim"; 152 153 power-domains = <&rpmhpd SDM845_CX>; 154 155 resets = <&gcc GCC_CDSP_RESTART>; 156 reset-names = "restart"; 157 158 qcom,halt-regs = <&tcsr 0x19004>; 159 160 memory-region = <&cdsp_fw_mem>; 161 162 qcom,smem-states = <&cdsp_smp2p_out 0>; 163 qcom,smem-state-names = "stop"; 164 }; 165