xref: /linux/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml (revision fc710de0dd25ed50a087833b4171eb1a46737a9e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/amd,bram-rproc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AMD MicroBlaze/V BRAM-based Remote Processor
8
9maintainers:
10  - Ben Levinsky <ben.levinsky@amd.com>
11
12description: |
13  Soft-core processor subsystem instantiated in AMD programmable logic and
14  using dual-port BRAM for firmware storage and execution.
15
16  Hardware Architecture:
17
18    Host (PS)                        Programmable Logic (PL)
19    =========                        ======================
20
21    AXI Interface -----------------> AXI BRAM Controller (Host Port)
22                                             |
23                                             | Port A
24                                             v
25                                     +-----------------+
26                                     |  Dual-Port BRAM |
27                                     | (shared memory) |
28                                     +-----------------+
29                                             ^
30                                             | Port B
31                                             |
32                                     AXI BRAM Controller (Soft-core Port)
33                                             ^
34                                             | LMB
35                                             |
36                                     Soft-core CPU (MicroBlaze/V)
37
38    GPIO --------------------------> Proc Sys Reset ----> CPU Reset Signal
39
40    Clock -------------------------> Clock Distribution -> CPU Clock
41
42  Memory Architecture:
43
44    The dual-port BRAM allows simultaneous access from both processors:
45      - Port A: Connected to the host AXI BRAM controller for firmware loading
46      - Port B: Connected to the soft-core local memory bus for execution
47
48  The reg property describes the executable BRAM window in the processor-local
49  address space. The parent bus node translates that window to the system
50  physical address space by using standard devicetree address translation
51  through ranges. A clock input and a reset GPIO control the subsystem.
52
53properties:
54  compatible:
55    oneOf:
56      - const: xlnx,zynqmp-bram-rproc
57      - items:
58          - enum:
59              - amd,versal2-bram-rproc
60              - xlnx,versal-bram-rproc
61              - xlnx,versal-net-bram-rproc
62          - const: xlnx,zynqmp-bram-rproc
63
64  reg:
65    maxItems: 1
66    description:
67      Processor-local address and size of the BRAM firmware memory window,
68      as seen by the soft-core processor (typically 0x0 for reset vector).
69      The parent bus ranges property must translate this window to the
70      corresponding system physical address.
71
72  clocks:
73    maxItems: 1
74    description:
75      Clock input for the soft-core processor subsystem.
76
77  firmware-name:
78    maxItems: 1
79    description:
80      Name of the firmware ELF file to load.
81
82  reset-gpios:
83    maxItems: 1
84    description:
85      GPIO specifier controlling the soft-core reset input.
86
87required:
88  - compatible
89  - reg
90  - clocks
91  - reset-gpios
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/gpio/gpio.h>
98    remoteproc@0 {
99      compatible = "xlnx,zynqmp-bram-rproc";
100      reg = <0x0 0x40000>;
101      clocks = <&pl_clk>;
102      firmware-name = "firmware.elf";
103      reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
104    };
105...
106