xref: /linux/Documentation/devicetree/bindings/power/reset/ti,keystone-reset.yaml (revision c6cf4441a3a05bb7273ed022f3e56c4fc591da08) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/reset/ti,keystone-reset.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI Keystone SoC Reset Controller
8
9maintainers:
10  - Andrew Davis <afd@ti.com>
11
12description:
13  This is intended to allow SoC reset in case of software reset of selected
14  watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset
15  SoC. Each watchdog timer event input is connected to the Reset Mux block. The
16  Reset Mux block can be configured to cause reset or not. Additionally soft or
17  hard reset can be configured.
18
19properties:
20  compatible:
21    const: ti,keystone-reset
22
23  reg:
24    maxItems: 1
25
26  ti,syscon-pll:
27    $ref: /schemas/types.yaml#/definitions/phandle-array
28    description:
29      The phandle to syscon used to access pll controller registers and the
30      offset to use reset control registers.
31    items:
32      - items:
33          - description: phandle to pll controller syscon
34          - description: offset within pll controller register space
35
36  ti,syscon-dev:
37    $ref: /schemas/types.yaml#/definitions/phandle-array
38    description:
39      The phandle to syscon used to access device state control registers and
40      the offset in order to use mux block registers for all watchdogs.
41    items:
42      - items:
43          - description: phandle to device state control syscon
44          - description: offset within device state control register
45
46  ti,soft-reset:
47    type: boolean
48    description:
49      Boolean option indicating soft reset. By default hard reset is used.
50
51  ti,wdt-list:
52    $ref: /schemas/types.yaml#/definitions/uint32-array
53    description:
54      WDT list that can cause SoC reset. It's not related to WDT driver, it's
55      just needed to enable a SoC related reset that's triggered by one of
56      WDTs. The list is in format- <0>, <2>; It can be in random order and
57      begins from 0 to 3, as keystone can contain up to 4 SoC reset watchdogs
58      and can be in random order.
59    minItems: 1
60    maxItems: 4
61    items:
62      minimum: 0
63      maximum: 3
64
65required:
66  - compatible
67  - reg
68  - ti,syscon-pll
69  - ti,syscon-dev
70
71additionalProperties: false
72
73examples:
74  - |
75    reset-controller@328 {
76        compatible = "ti,keystone-reset";
77        reg = <0x328 0x10>;
78        ti,syscon-pll = <&pllctrl 0xe4>;
79        ti,syscon-dev = <&devctrl 0x328>;
80        ti,wdt-list = <0>;
81    };
82