xref: /linux/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1*dac30db9SJia Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*dac30db9SJia Wang%YAML 1.2
3*dac30db9SJia Wang---
4*dac30db9SJia Wang$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml#
5*dac30db9SJia Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6*dac30db9SJia Wang
7*dac30db9SJia Wangtitle: UltraRISC DP1000 Pin Controller
8*dac30db9SJia Wang
9*dac30db9SJia Wangmaintainers:
10*dac30db9SJia Wang  - Jia Wang <wangjia@ultrarisc.com>
11*dac30db9SJia Wang
12*dac30db9SJia Wangdescription: |
13*dac30db9SJia Wang  UltraRISC RISC-V SoC DP1000 pin controller.
14*dac30db9SJia Wang  The controller manages ports A, B, C, D and LPC. Ports A-D default to
15*dac30db9SJia Wang  GPIO and provide additional SPI, UART, I2C, and PWM mux functions.
16*dac30db9SJia Wang  LPC pins default to the LPC interface and can be muxed to eSPI.
17*dac30db9SJia Wang  All pins also support pin configuration, including drive strength,
18*dac30db9SJia Wang  pull-up, and pull-down settings.
19*dac30db9SJia Wang
20*dac30db9SJia Wangproperties:
21*dac30db9SJia Wang  compatible:
22*dac30db9SJia Wang    const: ultrarisc,dp1000-pinctrl
23*dac30db9SJia Wang
24*dac30db9SJia Wang  reg:
25*dac30db9SJia Wang    items:
26*dac30db9SJia Wang      - description: pin controller registers
27*dac30db9SJia Wang
28*dac30db9SJia Wangrequired:
29*dac30db9SJia Wang  - compatible
30*dac30db9SJia Wang  - reg
31*dac30db9SJia Wang
32*dac30db9SJia WangpatternProperties:
33*dac30db9SJia Wang  '.*-pins$':
34*dac30db9SJia Wang    type: object
35*dac30db9SJia Wang    unevaluatedProperties: false
36*dac30db9SJia Wang    allOf:
37*dac30db9SJia Wang      - $ref: /schemas/pinctrl/pincfg-node.yaml#
38*dac30db9SJia Wang      - $ref: /schemas/pinctrl/pinmux-node.yaml#
39*dac30db9SJia Wang      - if:
40*dac30db9SJia Wang          properties:
41*dac30db9SJia Wang            pins:
42*dac30db9SJia Wang              items:
43*dac30db9SJia Wang                minimum: 40
44*dac30db9SJia Wang                maximum: 52
45*dac30db9SJia Wang        then:
46*dac30db9SJia Wang          properties:
47*dac30db9SJia Wang            function:
48*dac30db9SJia Wang              enum:
49*dac30db9SJia Wang                - lpc
50*dac30db9SJia Wang                - espi
51*dac30db9SJia Wang        else:
52*dac30db9SJia Wang          properties:
53*dac30db9SJia Wang            pins:
54*dac30db9SJia Wang              items:
55*dac30db9SJia Wang                maximum: 39
56*dac30db9SJia Wang            function:
57*dac30db9SJia Wang              enum:
58*dac30db9SJia Wang                - gpio
59*dac30db9SJia Wang                - i2c
60*dac30db9SJia Wang                - pwm
61*dac30db9SJia Wang                - spi
62*dac30db9SJia Wang                - uart
63*dac30db9SJia Wang
64*dac30db9SJia Wang    properties:
65*dac30db9SJia Wang      pins:
66*dac30db9SJia Wang        description: |
67*dac30db9SJia Wang          List of pins affected by this state node, using numeric pin IDs.
68*dac30db9SJia Wang          Pins 0-39 correspond to ports A-D, and pins 40-52 correspond
69*dac30db9SJia Wang          to LPC0-LPC12.
70*dac30db9SJia Wang        $ref: /schemas/types.yaml#/definitions/uint32-array
71*dac30db9SJia Wang        minItems: 1
72*dac30db9SJia Wang        uniqueItems: true
73*dac30db9SJia Wang        items:
74*dac30db9SJia Wang          minimum: 0
75*dac30db9SJia Wang          maximum: 52
76*dac30db9SJia Wang
77*dac30db9SJia Wang      function:
78*dac30db9SJia Wang        description: |
79*dac30db9SJia Wang          Mux function to select for the listed pins. Supported functions
80*dac30db9SJia Wang          depend on the selected pins and match the DP1000 hardware mux
81*dac30db9SJia Wang          table.
82*dac30db9SJia Wang        enum:
83*dac30db9SJia Wang          - gpio
84*dac30db9SJia Wang          - i2c
85*dac30db9SJia Wang          - pwm
86*dac30db9SJia Wang          - spi
87*dac30db9SJia Wang          - uart
88*dac30db9SJia Wang          - lpc
89*dac30db9SJia Wang          - espi
90*dac30db9SJia Wang
91*dac30db9SJia Wang      bias-disable: true
92*dac30db9SJia Wang      bias-high-impedance: true
93*dac30db9SJia Wang      bias-pull-up: true
94*dac30db9SJia Wang      bias-pull-down: true
95*dac30db9SJia Wang
96*dac30db9SJia Wang      drive-strength:
97*dac30db9SJia Wang        description: Output drive strength in mA.
98*dac30db9SJia Wang        enum: [20, 27, 33, 40]
99*dac30db9SJia Wang
100*dac30db9SJia Wang    required:
101*dac30db9SJia Wang      - pins
102*dac30db9SJia Wang      - function
103*dac30db9SJia Wang
104*dac30db9SJia WangunevaluatedProperties: false
105*dac30db9SJia Wang
106*dac30db9SJia Wangexamples:
107*dac30db9SJia Wang  - |
108*dac30db9SJia Wang    soc {
109*dac30db9SJia Wang      #address-cells = <2>;
110*dac30db9SJia Wang      #size-cells = <2>;
111*dac30db9SJia Wang
112*dac30db9SJia Wang      pinctrl@11081000 {
113*dac30db9SJia Wang        compatible = "ultrarisc,dp1000-pinctrl";
114*dac30db9SJia Wang        reg = <0x0 0x11081000 0x0 0x1000>;
115*dac30db9SJia Wang
116*dac30db9SJia Wang        i2c0-pins {
117*dac30db9SJia Wang          pins = <12 13>;
118*dac30db9SJia Wang          function = "i2c";
119*dac30db9SJia Wang          bias-pull-up;
120*dac30db9SJia Wang          drive-strength = <33>;
121*dac30db9SJia Wang        };
122*dac30db9SJia Wang
123*dac30db9SJia Wang        uart0-pins {
124*dac30db9SJia Wang          pins = <8 9>;
125*dac30db9SJia Wang          function = "uart";
126*dac30db9SJia Wang          bias-pull-up;
127*dac30db9SJia Wang          drive-strength = <33>;
128*dac30db9SJia Wang        };
129*dac30db9SJia Wang      };
130*dac30db9SJia Wang    };
131