xref: /linux/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2025.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 Hardware Debug Port Mux/Config
9
10maintainers:
11  - Clément LE GOFFIC <legoffic.clement@gmail.com>
12
13description:
14  STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP).
15  It allows to output internal signals on SoC's GPIO.
16
17properties:
18  compatible:
19    enum:
20      - st,stm32mp131-hdp
21      - st,stm32mp151-hdp
22      - st,stm32mp251-hdp
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    maxItems: 1
29
30  access-controllers:
31    minItems: 1
32    items:
33      - description: debug configuration access controller
34      - description: access controller that manages the HDP as a peripheral
35
36patternProperties:
37  "^hdp[0-7]-pins$":
38    type: object
39    $ref: pinmux-node.yaml#
40    additionalProperties: false
41
42    properties:
43      pins:
44        pattern: '^HDP[0-7]$'
45
46      function: true
47
48    required:
49      - function
50      - pins
51
52allOf:
53  - $ref: pinctrl.yaml#
54  - if:
55      properties:
56        compatible:
57          contains:
58            const: st,stm32mp131-hdp
59    then:
60      patternProperties:
61        "^hdp[0-7]-pins$":
62          properties:
63            function:
64              enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore,
65                      bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req,
66                      pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0,
67                      pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr,
68                      bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req,
69                      ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1,
70                      pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i,
71                      bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete,
72                      ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act,
73                      nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req,
74                      ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis,
75                      rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0,
76                      dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready,
77                      nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i,
78                      ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
79                      eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1,
80                      ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg,
81                      nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2,
82                      pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok,
83                      bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o,
84                      ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2,
85                      pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5,
86                      ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det,
87                      bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1,
88                      ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3,
89                      saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6,
90                      ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok,
91                      bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0,
92                      ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4,
93                      rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ]
94  - if:
95      properties:
96        compatible:
97          contains:
98            const: st,stm32mp151-hdp
99    then:
100      patternProperties:
101        "^hdp[0-7]-pins$":
102          properties:
103            function:
104              enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore,
105                      bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req,
106                      pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted,
107                      ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup,
108                      rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr,
109                      gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1,
110                      bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5,
111                      ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh,
112                      ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0,
113                      ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4,
114                      ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0,
115                      dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1,
116                      ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
117                      eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1,
118                      ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2,
119                      pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok,
120                      bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc,
121                      ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5,
122                      ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1,
123                      bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc,
124                      ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6,
125                      ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok,
126                      bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc,
127                      ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ]
128  - if:
129      properties:
130        compatible:
131          contains:
132            const: st,stm32mp251-hdp
133    then:
134      patternProperties:
135        "^hdp[0-7]-pins$":
136          properties:
137            function:
138              enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan,
139                      bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7,
140                      ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep,
141                      d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0,
142                      pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2,
143                      cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup,
144                      rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req,
145                      cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1,
146                      pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1,
147                      cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup,
148                      rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev,
149                      hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2,
150                      pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu,
151                      cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup,
152                      cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev,
153                      hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3,
154                      pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore,
155                      cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup,
156                      eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping,
157                      hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4,
158                      pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2,
159                      none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o,
160                      gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1,
161                      d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5,
162                      pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1,
163                      cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm,
164                      exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete,
165                      ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6,
166                      pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0,
167                      cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup,
168                      eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1,
169                      lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7,
170                      pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ]
171
172required:
173  - compatible
174  - reg
175  - clocks
176
177additionalProperties: false
178
179examples:
180  - |
181    #include <dt-bindings/clock/stm32mp1-clks.h>
182
183    pinctrl@54090000 {
184      compatible = "st,stm32mp151-hdp";
185      reg = <0x54090000 0x400>;
186      clocks = <&rcc HDP>;
187      pinctrl-names = "default";
188      pinctrl-0 = <&hdp2_gpo>;
189      hdp2_gpo: hdp2-pins {
190        function = "gpoval2";
191        pins = "HDP2";
192      };
193    };
194