1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2025. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 Hardware Debug Port Mux/Config 9 10maintainers: 11 - Clément LE GOFFIC <legoffic.clement@gmail.com> 12 13description: 14 STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP). 15 It allows to output internal signals on SoC's GPIO. 16 17properties: 18 compatible: 19 enum: 20 - st,stm32mp131-hdp 21 - st,stm32mp151-hdp 22 - st,stm32mp251-hdp 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 maxItems: 1 29 30patternProperties: 31 "^hdp[0-7]-pins$": 32 type: object 33 $ref: pinmux-node.yaml# 34 additionalProperties: false 35 36 properties: 37 pins: 38 pattern: '^HDP[0-7]$' 39 40 function: true 41 42 required: 43 - function 44 - pins 45 46allOf: 47 - $ref: pinctrl.yaml# 48 - if: 49 properties: 50 compatible: 51 contains: 52 const: st,stm32mp131-hdp 53 then: 54 patternProperties: 55 "^hdp[0-7]-pins$": 56 properties: 57 function: 58 enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore, 59 bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req, 60 pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0, 61 pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr, 62 bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req, 63 ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1, 64 pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i, 65 bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete, 66 ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act, 67 nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req, 68 ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis, 69 rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0, 70 dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready, 71 nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i, 72 ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable, 73 eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1, 74 ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg, 75 nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2, 76 pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok, 77 bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o, 78 ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, 79 pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5, 80 ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det, 81 bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1, 82 ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, 83 saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6, 84 ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok, 85 bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0, 86 ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, 87 rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ] 88 - if: 89 properties: 90 compatible: 91 contains: 92 const: st,stm32mp151-hdp 93 then: 94 patternProperties: 95 "^hdp[0-7]-pins$": 96 properties: 97 function: 98 enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore, 99 bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req, 100 pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted, 101 ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup, 102 rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr, 103 gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1, 104 bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5, 105 ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh, 106 ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0, 107 ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4, 108 ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0, 109 dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1, 110 ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable, 111 eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1, 112 ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2, 113 pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok, 114 bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc, 115 ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5, 116 ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1, 117 bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc, 118 ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6, 119 ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok, 120 bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc, 121 ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ] 122 - if: 123 properties: 124 compatible: 125 contains: 126 const: st,stm32mp251-hdp 127 then: 128 patternProperties: 129 "^hdp[0-7]-pins$": 130 properties: 131 function: 132 enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan, 133 bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7, 134 ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep, 135 d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0, 136 pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2, 137 cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup, 138 rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req, 139 cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1, 140 pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1, 141 cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup, 142 rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev, 143 hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2, 144 pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu, 145 cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup, 146 cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev, 147 hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3, 148 pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore, 149 cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup, 150 eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping, 151 hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4, 152 pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2, 153 none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o, 154 gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1, 155 d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5, 156 pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1, 157 cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm, 158 exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete, 159 ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6, 160 pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0, 161 cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup, 162 eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1, 163 lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7, 164 pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ] 165 166required: 167 - compatible 168 - reg 169 - clocks 170 171additionalProperties: false 172 173examples: 174 - | 175 #include <dt-bindings/clock/stm32mp1-clks.h> 176 177 pinctrl@54090000 { 178 compatible = "st,stm32mp151-hdp"; 179 reg = <0x54090000 0x400>; 180 clocks = <&rcc HDP>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&hdp2_gpo>; 183 hdp2_gpo: hdp2-pins { 184 function = "gpoval2"; 185 pins = "HDP2"; 186 }; 187 }; 188