xref: /linux/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml (revision faeab166167f5787719eb8683661fd41a3bb1514)
1*f6ea7004STzuyi Chang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*f6ea7004STzuyi Chang# Copyright 2025 Realtek Semiconductor Corporation
3*f6ea7004STzuyi Chang%YAML 1.2
4*f6ea7004STzuyi Chang---
5*f6ea7004STzuyi Chang$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml#
6*f6ea7004STzuyi Chang$schema: http://devicetree.org/meta-schemas/core.yaml#
7*f6ea7004STzuyi Chang
8*f6ea7004STzuyi Changtitle: Realtek DHC RTD1625 Pin Controller
9*f6ea7004STzuyi Chang
10*f6ea7004STzuyi Changmaintainers:
11*f6ea7004STzuyi Chang  - Tzuyi Chang <tychang@realtek.com>
12*f6ea7004STzuyi Chang  - Yu-Chun Lin <eleanor.lin@realtek.com>
13*f6ea7004STzuyi Chang
14*f6ea7004STzuyi Changdescription:
15*f6ea7004STzuyi Chang  The Realtek DHC RTD1625 is a high-definition media processor SoC. The
16*f6ea7004STzuyi Chang  RTD1625 pin controller is used to control pin function, pull-up/down
17*f6ea7004STzuyi Chang  resistors, drive strength, slew rate, Schmitt trigger, power source
18*f6ea7004STzuyi Chang  (I/O output voltage), input threshold domain selection and a higher-VIL mode.
19*f6ea7004STzuyi Chang
20*f6ea7004STzuyi Changproperties:
21*f6ea7004STzuyi Chang  compatible:
22*f6ea7004STzuyi Chang    items:
23*f6ea7004STzuyi Chang      - enum:
24*f6ea7004STzuyi Chang          - realtek,rtd1625-iso-pinctrl
25*f6ea7004STzuyi Chang          - realtek,rtd1625-main2-pinctrl
26*f6ea7004STzuyi Chang          - realtek,rtd1625-isom-pinctrl
27*f6ea7004STzuyi Chang          - realtek,rtd1625-ve4-pinctrl
28*f6ea7004STzuyi Chang
29*f6ea7004STzuyi Chang  reg:
30*f6ea7004STzuyi Chang    maxItems: 1
31*f6ea7004STzuyi Chang
32*f6ea7004STzuyi ChangpatternProperties:
33*f6ea7004STzuyi Chang  '-pins$':
34*f6ea7004STzuyi Chang    type: object
35*f6ea7004STzuyi Chang    allOf:
36*f6ea7004STzuyi Chang      - $ref: pincfg-node.yaml#
37*f6ea7004STzuyi Chang      - $ref: pinmux-node.yaml#
38*f6ea7004STzuyi Chang
39*f6ea7004STzuyi Chang    properties:
40*f6ea7004STzuyi Chang      pins:
41*f6ea7004STzuyi Chang        items:
42*f6ea7004STzuyi Chang          enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6,
43*f6ea7004STzuyi Chang                 gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13,
44*f6ea7004STzuyi Chang                 gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20,
45*f6ea7004STzuyi Chang                 gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29,
46*f6ea7004STzuyi Chang                 gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40,
47*f6ea7004STzuyi Chang                 gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47,
48*f6ea7004STzuyi Chang                 gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54,
49*f6ea7004STzuyi Chang                 gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61,
50*f6ea7004STzuyi Chang                 gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80,
51*f6ea7004STzuyi Chang                 gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87,
52*f6ea7004STzuyi Chang                 gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94,
53*f6ea7004STzuyi Chang                 gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100,
54*f6ea7004STzuyi Chang                 gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106,
55*f6ea7004STzuyi Chang                 gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112,
56*f6ea7004STzuyi Chang                 gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133,
57*f6ea7004STzuyi Chang                 gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139,
58*f6ea7004STzuyi Chang                 gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145,
59*f6ea7004STzuyi Chang                 gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151,
60*f6ea7004STzuyi Chang                 gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157,
61*f6ea7004STzuyi Chang                 gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163,
62*f6ea7004STzuyi Chang                 gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en,
63*f6ea7004STzuyi Chang                 csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc,
64*f6ea7004STzuyi Chang                 ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk,
65*f6ea7004STzuyi Chang                 emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3,
66*f6ea7004STzuyi Chang                 emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7,
67*f6ea7004STzuyi Chang                 emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data,
68*f6ea7004STzuyi Chang                 hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel,
69*f6ea7004STzuyi Chang                 sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2,
70*f6ea7004STzuyi Chang                 ve4_uart_loc]
71*f6ea7004STzuyi Chang
72*f6ea7004STzuyi Chang      function:
73*f6ea7004STzuyi Chang        enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0,
74*f6ea7004STzuyi Chang               ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8,
75*f6ea7004STzuyi Chang               csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc,
76*f6ea7004STzuyi Chang               gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1,
77*f6ea7004STzuyi Chang               i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl,
78*f6ea7004STzuyi Chang               pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5,
79*f6ea7004STzuyi Chang               rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable,
80*f6ea7004STzuyi Chang               spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1,
81*f6ea7004STzuyi Chang               uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10,
82*f6ea7004STzuyi Chang               usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic,
83*f6ea7004STzuyi Chang               vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1,
84*f6ea7004STzuyi Chang               ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1,
85*f6ea7004STzuyi Chang               etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1,
86*f6ea7004STzuyi Chang               i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0,
87*f6ea7004STzuyi Chang               pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0,
88*f6ea7004STzuyi Chang               pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1,
89*f6ea7004STzuyi Chang               uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1,
90*f6ea7004STzuyi Chang               ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,
91*f6ea7004STzuyi Chang               aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2,
92*f6ea7004STzuyi Chang               aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2,
93*f6ea7004STzuyi Chang               aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0,
94*f6ea7004STzuyi Chang               pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2,
95*f6ea7004STzuyi Chang               scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2,
96*f6ea7004STzuyi Chang               ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0,
97*f6ea7004STzuyi Chang               pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable,
98*f6ea7004STzuyi Chang               arm_trace_debug_enable]
99*f6ea7004STzuyi Chang
100*f6ea7004STzuyi Chang      drive-strength:
101*f6ea7004STzuyi Chang        enum: [4, 8]
102*f6ea7004STzuyi Chang
103*f6ea7004STzuyi Chang      bias-pull-down: true
104*f6ea7004STzuyi Chang
105*f6ea7004STzuyi Chang      bias-pull-up: true
106*f6ea7004STzuyi Chang
107*f6ea7004STzuyi Chang      bias-disable: true
108*f6ea7004STzuyi Chang
109*f6ea7004STzuyi Chang      input-schmitt-enable: true
110*f6ea7004STzuyi Chang
111*f6ea7004STzuyi Chang      input-schmitt-disable: true
112*f6ea7004STzuyi Chang
113*f6ea7004STzuyi Chang      input-voltage-microvolt:
114*f6ea7004STzuyi Chang        description: |
115*f6ea7004STzuyi Chang          Select the input receiver voltage domain for the pin.
116*f6ea7004STzuyi Chang          Valid arguments are:
117*f6ea7004STzuyi Chang          - 1800000: 1.8V input logic level
118*f6ea7004STzuyi Chang          - 3300000: 3.3V input logic level
119*f6ea7004STzuyi Chang        enum: [1800000, 3300000]
120*f6ea7004STzuyi Chang
121*f6ea7004STzuyi Chang      drive-push-pull: true
122*f6ea7004STzuyi Chang
123*f6ea7004STzuyi Chang      power-source:
124*f6ea7004STzuyi Chang        description: |
125*f6ea7004STzuyi Chang          Valid arguments are described as below:
126*f6ea7004STzuyi Chang          0: power supply of 1.8V
127*f6ea7004STzuyi Chang          1: power supply of 3.3V
128*f6ea7004STzuyi Chang        enum: [0, 1]
129*f6ea7004STzuyi Chang
130*f6ea7004STzuyi Chang      slew-rate:
131*f6ea7004STzuyi Chang        description: |
132*f6ea7004STzuyi Chang          Valid arguments are described as below:
133*f6ea7004STzuyi Chang            1: ~1ns falling time
134*f6ea7004STzuyi Chang            10: ~10ns falling time
135*f6ea7004STzuyi Chang            20: ~20ns falling time
136*f6ea7004STzuyi Chang            30: ~30ns falling time
137*f6ea7004STzuyi Chang        enum: [1, 10, 20, 30]
138*f6ea7004STzuyi Chang
139*f6ea7004STzuyi Chang      realtek,drive-strength-p:
140*f6ea7004STzuyi Chang        description: |
141*f6ea7004STzuyi Chang          Some of pins can be driven using the P-MOS and N-MOS transistor to
142*f6ea7004STzuyi Chang          achieve finer adjustments. The block-diagram representation is as
143*f6ea7004STzuyi Chang          follows:
144*f6ea7004STzuyi Chang                         VDD
145*f6ea7004STzuyi Chang                          |
146*f6ea7004STzuyi Chang                      ||--+
147*f6ea7004STzuyi Chang               +-----o||     P-MOS-FET
148*f6ea7004STzuyi Chang               |      ||--+
149*f6ea7004STzuyi Chang          IN --+          +----- out
150*f6ea7004STzuyi Chang               |      ||--+
151*f6ea7004STzuyi Chang               +------||     N-MOS-FET
152*f6ea7004STzuyi Chang                      ||--+
153*f6ea7004STzuyi Chang                          |
154*f6ea7004STzuyi Chang                         GND
155*f6ea7004STzuyi Chang          The driving strength of the P-MOS/N-MOS transistors impacts the
156*f6ea7004STzuyi Chang          waveform's rise/fall times. Greater driving strength results in
157*f6ea7004STzuyi Chang          shorter rise/fall times. Each P-MOS and N-MOS transistor offers
158*f6ea7004STzuyi Chang          8 configurable levels (0 to 7), with higher values indicating
159*f6ea7004STzuyi Chang          greater driving strength, contributing to achieving the desired
160*f6ea7004STzuyi Chang          speed.
161*f6ea7004STzuyi Chang
162*f6ea7004STzuyi Chang          The realtek,drive-strength-p is used to control the driving strength
163*f6ea7004STzuyi Chang          of the P-MOS output.
164*f6ea7004STzuyi Chang
165*f6ea7004STzuyi Chang          This value is not a simple count of transistors. Instead, it
166*f6ea7004STzuyi Chang          represents a weighted configuration. There is a base driving
167*f6ea7004STzuyi Chang          capability (even at value 0), and each bit adds a different weight to
168*f6ea7004STzuyi Chang          the total strength. The resulting current is non-linear and varies
169*f6ea7004STzuyi Chang          significantly based on the IO voltage (1.8V vs 3.3V) and the specific
170*f6ea7004STzuyi Chang          pad group.
171*f6ea7004STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
172*f6ea7004STzuyi Chang        minimum: 0
173*f6ea7004STzuyi Chang        maximum: 7
174*f6ea7004STzuyi Chang
175*f6ea7004STzuyi Chang      realtek,drive-strength-n:
176*f6ea7004STzuyi Chang        description: |
177*f6ea7004STzuyi Chang          Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
178*f6ea7004STzuyi Chang          is used to control the driving strength of the N-MOS output.
179*f6ea7004STzuyi Chang
180*f6ea7004STzuyi Chang          This property uses the same weighted configuration logic where values
181*f6ea7004STzuyi Chang          0-7 represent non-linear strength adjustments rather than a transistor
182*f6ea7004STzuyi Chang          count.
183*f6ea7004STzuyi Chang
184*f6ea7004STzuyi Chang          Higher values indicate greater driving strength, resulting in shorter
185*f6ea7004STzuyi Chang          fall times.
186*f6ea7004STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
187*f6ea7004STzuyi Chang        minimum: 0
188*f6ea7004STzuyi Chang        maximum: 7
189*f6ea7004STzuyi Chang
190*f6ea7004STzuyi Chang      realtek,duty-cycle:
191*f6ea7004STzuyi Chang        description: |
192*f6ea7004STzuyi Chang          An integer describing the level to adjust the output pulse width, it
193*f6ea7004STzuyi Chang          provides a fixed nanosecond-level adjustment to the rising/falling
194*f6ea7004STzuyi Chang          edges of an existing signal. It is used for Signal Integrity tuning
195*f6ea7004STzuyi Chang          (adding/subtracting delay to fine-tune the high/low duration), rather
196*f6ea7004STzuyi Chang          than generating a specific PWM frequency.
197*f6ea7004STzuyi Chang
198*f6ea7004STzuyi Chang          Valid arguments are described as below:
199*f6ea7004STzuyi Chang          0: 0ns
200*f6ea7004STzuyi Chang          2: + 0.25ns
201*f6ea7004STzuyi Chang          3: + 0.5ns
202*f6ea7004STzuyi Chang          4: -0.25ns
203*f6ea7004STzuyi Chang          5: -0.5ns
204*f6ea7004STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
205*f6ea7004STzuyi Chang        enum: [0, 2, 3, 4, 5]
206*f6ea7004STzuyi Chang
207*f6ea7004STzuyi Chang      realtek,high-vil-microvolt:
208*f6ea7004STzuyi Chang        description: |
209*f6ea7004STzuyi Chang          The threshold value for the input receiver's LOW recognition (VIL).
210*f6ea7004STzuyi Chang
211*f6ea7004STzuyi Chang          This property is used to address specific HDMI I2C compatibility
212*f6ea7004STzuyi Chang          issues where some sinks (TVs) have weak pull-down capabilities and
213*f6ea7004STzuyi Chang          fail to pull the bus voltage below the standard VIL threshold
214*f6ea7004STzuyi Chang          (~0.7V).
215*f6ea7004STzuyi Chang
216*f6ea7004STzuyi Chang          Setting this property to 1100000 (1.1V) enables a specialized input
217*f6ea7004STzuyi Chang          receiver mode that raises the effective VIL threshold to improve
218*f6ea7004STzuyi Chang          detection.
219*f6ea7004STzuyi Chang        enum: [1100000]
220*f6ea7004STzuyi Chang
221*f6ea7004STzuyi Chang    required:
222*f6ea7004STzuyi Chang      - pins
223*f6ea7004STzuyi Chang
224*f6ea7004STzuyi Chang    additionalProperties: false
225*f6ea7004STzuyi Chang
226*f6ea7004STzuyi Changrequired:
227*f6ea7004STzuyi Chang  - compatible
228*f6ea7004STzuyi Chang  - reg
229*f6ea7004STzuyi Chang
230*f6ea7004STzuyi ChangadditionalProperties: false
231*f6ea7004STzuyi Chang
232*f6ea7004STzuyi Changexamples:
233*f6ea7004STzuyi Chang  - |
234*f6ea7004STzuyi Chang    pinctrl@4e000 {
235*f6ea7004STzuyi Chang        compatible = "realtek,rtd1625-iso-pinctrl";
236*f6ea7004STzuyi Chang        reg = <0x4e000 0x130>;
237*f6ea7004STzuyi Chang
238*f6ea7004STzuyi Chang        emmc-hs200-pins {
239*f6ea7004STzuyi Chang            pins = "emmc_clk",
240*f6ea7004STzuyi Chang                   "emmc_cmd",
241*f6ea7004STzuyi Chang                   "emmc_data_0",
242*f6ea7004STzuyi Chang                   "emmc_data_1",
243*f6ea7004STzuyi Chang                   "emmc_data_2",
244*f6ea7004STzuyi Chang                   "emmc_data_3",
245*f6ea7004STzuyi Chang                   "emmc_data_4",
246*f6ea7004STzuyi Chang                   "emmc_data_5",
247*f6ea7004STzuyi Chang                   "emmc_data_6",
248*f6ea7004STzuyi Chang                   "emmc_data_7";
249*f6ea7004STzuyi Chang            function = "emmc";
250*f6ea7004STzuyi Chang            realtek,drive-strength-p = <2>;
251*f6ea7004STzuyi Chang            realtek,drive-strength-n = <2>;
252*f6ea7004STzuyi Chang        };
253*f6ea7004STzuyi Chang
254*f6ea7004STzuyi Chang        i2c-0-pins {
255*f6ea7004STzuyi Chang            pins = "gpio_12",
256*f6ea7004STzuyi Chang                   "gpio_13";
257*f6ea7004STzuyi Chang            function = "i2c0";
258*f6ea7004STzuyi Chang            drive-strength = <4>;
259*f6ea7004STzuyi Chang        };
260*f6ea7004STzuyi Chang    };
261