1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright 2025 Realtek Semiconductor Corporation 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Realtek DHC RTD1625 Pin Controller 9 10maintainers: 11 - Tzuyi Chang <tychang@realtek.com> 12 - Yu-Chun Lin <eleanor.lin@realtek.com> 13 14description: 15 The Realtek DHC RTD1625 is a high-definition media processor SoC. The 16 RTD1625 pin controller is used to control pin function, pull-up/down 17 resistors, drive strength, slew rate, Schmitt trigger, power source 18 (I/O output voltage), input threshold domain selection and a higher-VIL mode. 19 20properties: 21 compatible: 22 items: 23 - enum: 24 - realtek,rtd1625-iso-pinctrl 25 - realtek,rtd1625-main2-pinctrl 26 - realtek,rtd1625-isom-pinctrl 27 - realtek,rtd1625-ve4-pinctrl 28 29 reg: 30 maxItems: 1 31 32patternProperties: 33 '-pins$': 34 type: object 35 allOf: 36 - $ref: pincfg-node.yaml# 37 - $ref: pinmux-node.yaml# 38 39 properties: 40 pins: 41 items: 42 enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, 43 gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, 44 gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, 45 gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29, 46 gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40, 47 gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, 48 gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54, 49 gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, 50 gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80, 51 gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87, 52 gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94, 53 gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100, 54 gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106, 55 gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112, 56 gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133, 57 gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139, 58 gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145, 59 gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151, 60 gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157, 61 gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163, 62 gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en, 63 csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc, 64 ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk, 65 emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3, 66 emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7, 67 emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data, 68 hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel, 69 sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2, 70 ve4_uart_loc] 71 72 function: 73 enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0, 74 ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8, 75 csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc, 76 gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1, 77 i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl, 78 pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5, 79 rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable, 80 spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1, 81 uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10, 82 usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic, 83 vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1, 84 ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1, 85 etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1, 86 i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0, 87 pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0, 88 pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1, 89 uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1, 90 ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, 91 aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2, 92 aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2, 93 aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0, 94 pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2, 95 scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2, 96 ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0, 97 pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable, 98 arm_trace_debug_enable] 99 100 drive-strength: 101 enum: [4, 8] 102 103 bias-pull-down: true 104 105 bias-pull-up: true 106 107 bias-disable: true 108 109 input-schmitt-enable: true 110 111 input-schmitt-disable: true 112 113 input-voltage-microvolt: 114 description: | 115 Select the input receiver voltage domain for the pin. 116 Valid arguments are: 117 - 1800000: 1.8V input logic level 118 - 3300000: 3.3V input logic level 119 enum: [1800000, 3300000] 120 121 drive-push-pull: true 122 123 power-source: 124 description: | 125 Valid arguments are described as below: 126 0: power supply of 1.8V 127 1: power supply of 3.3V 128 enum: [0, 1] 129 130 slew-rate: 131 description: | 132 Valid arguments are described as below: 133 1: ~1ns falling time 134 10: ~10ns falling time 135 20: ~20ns falling time 136 30: ~30ns falling time 137 enum: [1, 10, 20, 30] 138 139 realtek,drive-strength-p: 140 description: | 141 Some of pins can be driven using the P-MOS and N-MOS transistor to 142 achieve finer adjustments. The block-diagram representation is as 143 follows: 144 VDD 145 | 146 ||--+ 147 +-----o|| P-MOS-FET 148 | ||--+ 149 IN --+ +----- out 150 | ||--+ 151 +------|| N-MOS-FET 152 ||--+ 153 | 154 GND 155 The driving strength of the P-MOS/N-MOS transistors impacts the 156 waveform's rise/fall times. Greater driving strength results in 157 shorter rise/fall times. Each P-MOS and N-MOS transistor offers 158 8 configurable levels (0 to 7), with higher values indicating 159 greater driving strength, contributing to achieving the desired 160 speed. 161 162 The realtek,drive-strength-p is used to control the driving strength 163 of the P-MOS output. 164 165 This value is not a simple count of transistors. Instead, it 166 represents a weighted configuration. There is a base driving 167 capability (even at value 0), and each bit adds a different weight to 168 the total strength. The resulting current is non-linear and varies 169 significantly based on the IO voltage (1.8V vs 3.3V) and the specific 170 pad group. 171 $ref: /schemas/types.yaml#/definitions/uint32 172 minimum: 0 173 maximum: 7 174 175 realtek,drive-strength-n: 176 description: | 177 Similar to the realtek,drive-strength-p, the realtek,drive-strength-n 178 is used to control the driving strength of the N-MOS output. 179 180 This property uses the same weighted configuration logic where values 181 0-7 represent non-linear strength adjustments rather than a transistor 182 count. 183 184 Higher values indicate greater driving strength, resulting in shorter 185 fall times. 186 $ref: /schemas/types.yaml#/definitions/uint32 187 minimum: 0 188 maximum: 7 189 190 realtek,duty-cycle: 191 description: | 192 An integer describing the level to adjust the output pulse width, it 193 provides a fixed nanosecond-level adjustment to the rising/falling 194 edges of an existing signal. It is used for Signal Integrity tuning 195 (adding/subtracting delay to fine-tune the high/low duration), rather 196 than generating a specific PWM frequency. 197 198 Valid arguments are described as below: 199 0: 0ns 200 2: + 0.25ns 201 3: + 0.5ns 202 4: -0.25ns 203 5: -0.5ns 204 $ref: /schemas/types.yaml#/definitions/uint32 205 enum: [0, 2, 3, 4, 5] 206 207 realtek,high-vil-microvolt: 208 description: | 209 The threshold value for the input receiver's LOW recognition (VIL). 210 211 This property is used to address specific HDMI I2C compatibility 212 issues where some sinks (TVs) have weak pull-down capabilities and 213 fail to pull the bus voltage below the standard VIL threshold 214 (~0.7V). 215 216 Setting this property to 1100000 (1.1V) enables a specialized input 217 receiver mode that raises the effective VIL threshold to improve 218 detection. 219 enum: [1100000] 220 221 required: 222 - pins 223 224 additionalProperties: false 225 226required: 227 - compatible 228 - reg 229 230additionalProperties: false 231 232examples: 233 - | 234 pinctrl@4e000 { 235 compatible = "realtek,rtd1625-iso-pinctrl"; 236 reg = <0x4e000 0x130>; 237 238 emmc-hs200-pins { 239 pins = "emmc_clk", 240 "emmc_cmd", 241 "emmc_data_0", 242 "emmc_data_1", 243 "emmc_data_2", 244 "emmc_data_3", 245 "emmc_data_4", 246 "emmc_data_5", 247 "emmc_data_6", 248 "emmc_data_7"; 249 function = "emmc"; 250 realtek,drive-strength-p = <2>; 251 realtek,drive-strength-n = <2>; 252 }; 253 254 i2c-0-pins { 255 pins = "gpio_12", 256 "gpio_13"; 257 function = "i2c0"; 258 drive-strength = <4>; 259 }; 260 }; 261