1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SDM630 and SDM660 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 12 13description: 14 Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC. 15 16allOf: 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 18 19properties: 20 compatible: 21 enum: 22 - qcom,sdm630-pinctrl 23 - qcom,sdm660-pinctrl 24 25 reg: 26 maxItems: 3 27 28 reg-names: 29 items: 30 - const: south 31 - const: center 32 - const: north 33 34 interrupts: true 35 interrupt-controller: true 36 "#interrupt-cells": true 37 gpio-controller: true 38 39 gpio-reserved-ranges: 40 minItems: 1 41 maxItems: 57 42 43 gpio-line-names: 44 maxItems: 114 45 46 "#gpio-cells": true 47 gpio-ranges: true 48 wakeup-parent: true 49 50patternProperties: 51 "-state$": 52 oneOf: 53 - $ref: "#/$defs/qcom-sdm630-tlmm-state" 54 - patternProperties: 55 "-pins$": 56 $ref: "#/$defs/qcom-sdm630-tlmm-state" 57 additionalProperties: false 58 59$defs: 60 qcom-sdm630-tlmm-state: 61 type: object 62 description: 63 Pinctrl node's client devices use subnodes for desired pin configuration. 64 Client device subnodes use below standard properties. 65 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 66 67 properties: 68 pins: 69 description: 70 List of gpio pins affected by the properties specified in this 71 subnode. 72 items: 73 oneOf: 74 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$" 75 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, 76 sdc2_cmd, sdc2_data ] 77 minItems: 1 78 maxItems: 36 79 80 function: 81 description: 82 Specify the alternative function to be configured for the specified 83 pins. 84 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, 85 atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1, 86 atest_tsens, atest_tsens2, atest_usb1, atest_usb10, 87 atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, 88 atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0, 89 bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, 90 blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b, 91 blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, 92 blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a, 93 blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, 94 blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1, 95 blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c, 96 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1, 97 gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c, 98 isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync, 99 mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte, 100 nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0, 101 phase_flag1, phase_flag10, phase_flag11, phase_flag12, 102 phase_flag13, phase_flag14, phase_flag15, phase_flag16, 103 phase_flag17, phase_flag18, phase_flag19, phase_flag2, 104 phase_flag20, phase_flag21, phase_flag22, phase_flag23, 105 phase_flag24, phase_flag25, phase_flag26, phase_flag27, 106 phase_flag28, phase_flag29, phase_flag3, phase_flag30, 107 phase_flag31, phase_flag4, phase_flag5, phase_flag6, 108 phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset, 109 pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem, 110 pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b, 111 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, 112 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2, 113 qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, 114 qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk, 115 qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3, 116 qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu, 117 ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk, 118 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, 119 uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout, 120 vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, 121 wlan1_adc1, wlan2_adc0, wlan2_adc1 ] 122 123 bias-disable: true 124 bias-pull-down: true 125 bias-pull-up: true 126 drive-strength: true 127 input-enable: true 128 output-high: true 129 output-low: true 130 131 required: 132 - pins 133 134 additionalProperties: false 135 136required: 137 - compatible 138 - reg 139 140additionalProperties: false 141 142examples: 143 - | 144 #include <dt-bindings/interrupt-controller/arm-gic.h> 145 146 tlmm: pinctrl@3100000 { 147 compatible = "qcom,sdm630-pinctrl"; 148 reg = <0x03100000 0x400000>, 149 <0x03500000 0x400000>, 150 <0x03900000 0x400000>; 151 reg-names = "south", "center", "north"; 152 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 153 gpio-controller; 154 gpio-ranges = <&tlmm 0 0 114>; 155 #gpio-cells = <2>; 156 interrupt-controller; 157 #interrupt-cells = <2>; 158 159 blsp1-uart1-default-state { 160 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 161 function = "gpio"; 162 drive-strength = <2>; 163 bias-disable; 164 }; 165 166 blsp2_uart1_default: blsp2-uart1-active-state { 167 tx-rts-pins { 168 pins = "gpio16", "gpio19"; 169 function = "blsp_uart5"; 170 drive-strength = <2>; 171 bias-disable; 172 }; 173 174 rx-pins { 175 pins = "gpio17"; 176 function = "blsp_uart5"; 177 drive-strength = <2>; 178 bias-pull-up; 179 }; 180 181 cts-pins { 182 pins = "gpio18"; 183 function = "blsp_uart5"; 184 drive-strength = <2>; 185 bias-pull-down; 186 }; 187 }; 188 }; 189