xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SA8797P TLMM block

maintainers:
  - Bartosz Golaszewski <brgl@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,nord-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 90

  gpio-line-names:
    maxItems: 181

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-nord-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-nord-tlmm-state"
        additionalProperties: false

$defs:
  qcom-nord-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$"
            - enum: [ ufs_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,
                aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,
                aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,
                aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,
                aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,
                aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,
                aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,
                aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,
                aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,
                aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,
                aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,
                aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,
                aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,
                aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,
                bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,
                clink_debug, dbg_out, dbg_out_clk,
                ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
                ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,
                dp_rx11, dp_rx1_mute,
                edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,
                edp3_hot, edp3_lcd,
                emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,
                emac1_mdc, emac1_mdio, emac1_ptp,
                gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,
                gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,
                mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,
                mdp_vsync_p, mdp_vsync_s,
                pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,
                pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
                prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,
                qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
                qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,
                qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
                qup2_se5, qup2_se6,
                sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,
                smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,
                tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,
                usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,
                usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]

    required:
      - pins

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@f100000 {
        compatible = "qcom,nord-tlmm";
        reg = <0x0f100000 0xc0000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 181>;
        wakeup-parent = <&pdc>;

        qup_uart15_default: qup-uart15-default-state {
            pins = "gpio147", "gpio148";
            function = "qup2_se2";
            drive-strength = <2>;
            bias-disable;
        };
    };
...