xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SA8797P TLMM block
8
9maintainers:
10  - Bartosz Golaszewski <brgl@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,nord-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges:
29    minItems: 1
30    maxItems: 90
31
32  gpio-line-names:
33    maxItems: 181
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-nord-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-nord-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-nord-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$"
61            - enum: [ ufs_reset ]
62        minItems: 1
63        maxItems: 16
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70        enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,
71                aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,
72                aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,
73                aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,
74                aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,
75                aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,
76                aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,
77                aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,
78                aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,
79                aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,
80                aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,
81                aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,
82                aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,
83                aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,
84                bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,
85                clink_debug, dbg_out, dbg_out_clk,
86                ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
87                ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,
88                dp_rx11, dp_rx1_mute,
89                edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,
90                edp3_hot, edp3_lcd,
91                emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,
92                emac1_mdc, emac1_mdio, emac1_ptp,
93                gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,
94                gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,
95                mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,
96                mdp_vsync_p, mdp_vsync_s,
97                pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,
98                pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
99                prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,
100                qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
101                qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,
102                qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
103                qup2_se5, qup2_se6,
104                sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,
105                smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,
106                tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,
107                usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,
108                usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]
109
110    required:
111      - pins
112
113required:
114  - compatible
115  - reg
116
117unevaluatedProperties: false
118
119examples:
120  - |
121    #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123    tlmm: pinctrl@f100000 {
124        compatible = "qcom,nord-tlmm";
125        reg = <0x0f100000 0xc0000>;
126        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127        gpio-controller;
128        #gpio-cells = <2>;
129        interrupt-controller;
130        #interrupt-cells = <2>;
131        gpio-ranges = <&tlmm 0 0 181>;
132        wakeup-parent = <&pdc>;
133
134        qup_uart15_default: qup-uart15-default-state {
135            pins = "gpio147", "gpio148";
136            function = "qup2_se2";
137            drive-strength = <2>;
138            bias-disable;
139        };
140    };
141...
142