xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml (revision 637315cb400eed1dbe721954fea437a61a2d65b2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6350 SoC LPASS LPI TLMM
8
9maintainers:
10  - Luca Weiss <luca.weiss@fairphone.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14  (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC.
15
16properties:
17  compatible:
18    const: qcom,sm6350-lpass-lpi-pinctrl
19
20  reg:
21    items:
22      - description: LPASS LPI TLMM Control and Status registers
23      - description: LPASS LPI MCC registers
24
25  clocks:
26    items:
27      - description: LPASS Core voting clock
28      - description: LPASS Audio voting clock
29
30  clock-names:
31    items:
32      - const: core
33      - const: audio
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-sm6350-lpass-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-sm6350-lpass-state"
42        additionalProperties: false
43
44$defs:
45  qcom-sm6350-lpass-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          pattern: "^gpio([0-9]|1[0-4])$"
60
61      function:
62        enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
63                dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
64                i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,
65                swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
66                wsa_swr_data ]
67        description:
68          Specify the alternative function to be configured for the specified
69          pins.
70
71allOf:
72  - $ref: qcom,lpass-lpi-common.yaml#
73
74required:
75  - compatible
76  - reg
77  - clocks
78  - clock-names
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
85
86    lpass_tlmm: pinctrl@33c0000 {
87        compatible = "qcom,sm6350-lpass-lpi-pinctrl";
88        reg = <0x033c0000 0x20000>,
89              <0x03550000 0x10000>;
90        gpio-controller;
91        #gpio-cells = <2>;
92        gpio-ranges = <&lpass_tlmm 0 0 15>;
93
94        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
95                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
96        clock-names = "core",
97                      "audio";
98
99        i2s1_active: i2s1-active-state {
100            clk-pins {
101                pins = "gpio6";
102                function = "i2s1_clk";
103                drive-strength = <8>;
104                bias-disable;
105                output-high;
106            };
107
108            ws-pins {
109                pins = "gpio7";
110                function = "i2s1_ws";
111                drive-strength = <8>;
112                bias-disable;
113                output-high;
114            };
115
116            data-pins {
117                pins = "gpio8", "gpio9";
118                function = "i2s1_data";
119                drive-strength = <8>;
120                bias-disable;
121                output-high;
122            };
123        };
124    };
125