xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Shikra TLMM block
8
9maintainers:
10  - Komal Bajaj <komal.bajaj@oss.qualcomm.com>
11
12description: |
13  Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,shikra-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges:
29    minItems: 1
30    maxItems: 83
31
32  gpio-line-names:
33    maxItems: 166
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-shikra-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-shikra-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-shikra-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$"
61            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
62                      sdc2_clk, sdc2_cmd, sdc2_data ]
63        minItems: 1
64        maxItems: 36
65
66      function:
67        description:
68          Specify the alternative function to be configured for the specified
69          pins.
70
71        enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,
72                atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,
73                cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,
74                dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,
75                emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,
76                emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,
77                i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,
78                mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,
79                nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,
80                phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,
81                qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,
82                qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,
83                qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,
84                qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,
85                ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,
86                tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,
87                vfr, vsense_trigger_mirnat, wlan ]
88
89    required:
90      - pins
91
92required:
93  - compatible
94  - reg
95
96unevaluatedProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/interrupt-controller/arm-gic.h>
101
102    tlmm: pinctrl@500000 {
103        compatible = "qcom,shikra-tlmm";
104        reg = <0x00500000 0x800000>;
105
106        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
107
108        gpio-controller;
109        #gpio-cells = <2>;
110
111        interrupt-controller;
112        #interrupt-cells = <2>;
113
114        gpio-ranges = <&tlmm 0 0 166>;
115
116        qup-uart0-default-state {
117            pins = "gpio0", "gpio1";
118            function = "qup0_se1";
119            drive-strength = <2>;
120            bias-disable;
121        };
122    };
123...
124