xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ9650 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,ipq9650-tlmm
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  gpio-reserved-ranges:
30    minItems: 1
31    maxItems: 27
32
33  gpio-line-names:
34    maxItems: 54
35
36patternProperties:
37  "-state$":
38    oneOf:
39      - $ref: "#/$defs/qcom-ipq9650-tlmm-state"
40      - patternProperties:
41          "-pins$":
42            $ref: "#/$defs/qcom-ipq9650-tlmm-state"
43        additionalProperties: false
44
45$defs:
46  qcom-ipq9650-tlmm-state:
47    type: object
48    description:
49      Pinctrl node's client devices use subnodes for desired pin configuration.
50      Client device subnodes use below standard properties.
51    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52    unevaluatedProperties: false
53
54    properties:
55      pins:
56        description:
57          List of gpio pins affected by the properties specified in this
58          subnode.
59        items:
60          pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
61        minItems: 1
62        maxItems: 36
63
64      function:
65        description:
66          Specify the alternative function to be configured for the specified
67          pins.
68
69        enum: [ atest_char_start, atest_char_status0, atest_char_status1,
70                atest_char_status2, atest_char_status3, atest_tic_en,
71                audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1,
72                audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0,
73                audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1,
74                core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3,
75                core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk,
76                gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio,
77                mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0,
78                mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n,
79                pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n,
80                pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync,
81                pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
82                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
83                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
84                qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data,
85                qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3,
86                qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1,
87                rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ]
88
89    required:
90      - pins
91
92required:
93  - compatible
94  - reg
95
96unevaluatedProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/interrupt-controller/arm-gic.h>
101
102    tlmm: pinctrl@1000000 {
103        compatible = "qcom,ipq9650-tlmm";
104        reg = <0x01000000 0x300000>;
105        gpio-controller;
106        #gpio-cells = <2>;
107        gpio-ranges = <&tlmm 0 0 54>;
108        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
109        interrupt-controller;
110        #interrupt-cells = <2>;
111
112        qup-uart1-default-state {
113            pins = "gpio43", "gpio44";
114            function = "qup_se6";
115            drive-strength = <8>;
116            bias-pull-down;
117        };
118    };
119