1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm IPQ5210 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> 12 13description: 14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC. 15 16allOf: 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,ipq5210-tlmm 22 23 reg: 24 maxItems: 1 25 26 interrupts: 27 maxItems: 1 28 29 gpio-reserved-ranges: 30 minItems: 1 31 maxItems: 27 32 33 gpio-line-names: 34 maxItems: 54 35 36patternProperties: 37 "-state$": 38 oneOf: 39 - $ref: "#/$defs/qcom-ipq5210-tlmm-state" 40 - patternProperties: 41 "-pins$": 42 $ref: "#/$defs/qcom-ipq5210-tlmm-state" 43 additionalProperties: false 44 45$defs: 46 qcom-ipq5210-tlmm-state: 47 type: object 48 description: 49 Pinctrl node's client devices use subnodes for desired pin configuration. 50 Client device subnodes use below standard properties. 51 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 52 unevaluatedProperties: false 53 54 properties: 55 pins: 56 description: 57 List of gpio pins affected by the properties specified in this 58 subnode. 59 items: 60 pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" 61 minItems: 1 62 maxItems: 36 63 64 function: 65 description: 66 Specify the alternative function to be configured for the specified 67 pins. 68 69 enum: [ atest_char_start, atest_char_status0, atest_char_status1, 70 atest_char_status2, atest_char_status3, atest_tic_en, audio_pri, 71 audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1, 72 audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2, 73 audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec, 74 audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1, 75 audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2, 76 audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0, 77 cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out, 78 gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0, 79 led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, 80 mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, 81 pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test, 82 pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx, 83 pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, 84 gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0, 85 pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, 86 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, 87 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, 88 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, 89 qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2, 90 qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, 91 qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1, 92 rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ] 93 94 required: 95 - pins 96 97required: 98 - compatible 99 - reg 100 101unevaluatedProperties: false 102 103examples: 104 - | 105 #include <dt-bindings/interrupt-controller/arm-gic.h> 106 107 tlmm: pinctrl@1000000 { 108 compatible = "qcom,ipq5210-tlmm"; 109 reg = <0x01000000 0x300000>; 110 gpio-controller; 111 #gpio-cells = <0x2>; 112 gpio-ranges = <&tlmm 0 0 54>; 113 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-controller; 115 #interrupt-cells = <0x2>; 116 117 qup-uart1-default-state { 118 pins = "gpio38", "gpio39"; 119 function = "qup_se1"; 120 drive-strength = <6>; 121 bias-pull-down; 122 }; 123 }; 124