xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml (revision faeab166167f5787719eb8683661fd41a3bb1514) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Hawi TLMM block
8
9maintainers:
10  - Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,hawi-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges:
29    minItems: 1
30    maxItems: 113
31
32  gpio-line-names:
33    maxItems: 226
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-hawi-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-hawi-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-hawi-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
61            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
70                audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
71                cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
72                coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
73                dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
74                i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
75                ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
76                mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
77                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
78                modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
79                nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
80                phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
81                qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
82                qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
83                qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
84                qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
85                qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
86                qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
87                rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
88                sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
89                uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
90                wcn_sw_ctrl ]
91
92    required:
93      - pins
94
95required:
96  - compatible
97  - reg
98
99unevaluatedProperties: false
100
101examples:
102  - |
103    #include <dt-bindings/interrupt-controller/arm-gic.h>
104
105    tlmm: pinctrl@f100000 {
106        compatible = "qcom,hawi-tlmm";
107        reg = <0x0f100000 0x300000>;
108        interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
109        gpio-controller;
110        #gpio-cells = <2>;
111        gpio-ranges = <&tlmm 0 0 227>;
112        interrupt-controller;
113        #interrupt-cells = <2>;
114
115        qup-uart7-state {
116          pins = "gpio62", "gpio63";
117          function = "qup1_se7";
118        };
119    };
120...
121