1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. Glymur TLMM block 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,glymur-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: 26 maxItems: 1 27 28 gpio-reserved-ranges: 29 minItems: 1 30 maxItems: 125 31 32 gpio-line-names: 33 maxItems: 250 34 35patternProperties: 36 "-state$": 37 oneOf: 38 - $ref: "#/$defs/qcom-glymur-tlmm-state" 39 - patternProperties: 40 "-pins$": 41 $ref: "#/$defs/qcom-glymur-tlmm-state" 42 additionalProperties: false 43 44$defs: 45 qcom-glymur-tlmm-state: 46 type: object 47 description: 48 Pinctrl node's client devices use subnodes for desired pin configuration. 49 Client device subnodes use below standard properties. 50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 51 unevaluatedProperties: false 52 53 properties: 54 pins: 55 description: 56 List of gpio pins affected by the properties specified in this 57 subnode. 58 items: 59 oneOf: 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$" 61 - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] 62 minItems: 1 63 maxItems: 36 64 65 function: 66 description: 67 Specify the alternative function to be configured for the specified 68 pins. 69 enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb, 70 audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4, 71 cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, 72 cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete, 73 ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi, 74 edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en, 75 eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1, 76 gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda, 77 i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, 78 ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p, 79 mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk, 80 pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag, 81 pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc, 82 qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2, 83 qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7, 84 qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, 85 qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, 86 qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1, 87 sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n, 88 sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng, 89 tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx, 90 usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx, 91 usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx, 92 usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] 93 94 required: 95 - pins 96 97required: 98 - compatible 99 - reg 100 101unevaluatedProperties: false 102 103examples: 104 - | 105 #include <dt-bindings/interrupt-controller/arm-gic.h> 106 tlmm: pinctrl@f100000 { 107 compatible = "qcom,glymur-tlmm"; 108 reg = <0x0f100000 0xf00000>; 109 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 110 gpio-controller; 111 #gpio-cells = <2>; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 gpio-ranges = <&tlmm 0 0 249>; 115 wakeup-parent = <&pdc>; 116 gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>; 117 qup_uart21_default: qup-uart21-default-state { 118 tx-pins { 119 pins = "gpio86"; 120 function = "qup2_se5"; 121 drive-strength = <2>; 122 bias-disable; 123 }; 124 125 rx-pins { 126 pins = "gpio87"; 127 function = "qup2_se5"; 128 drive-strength = <2>; 129 bias-disable; 130 }; 131 }; 132 }; 133... 134