1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. Eliza TLMM block 8 9maintainers: 10 - Abel Vesa <abel.vesa@oss.qualcomm.com> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,eliza-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: 26 maxItems: 1 27 28 gpio-reserved-ranges: 29 minItems: 1 30 maxItems: 93 31 32 gpio-line-names: 33 maxItems: 185 34 35patternProperties: 36 "-state$": 37 oneOf: 38 - $ref: "#/$defs/qcom-eliza-tlmm-state" 39 - patternProperties: 40 "-pins$": 41 $ref: "#/$defs/qcom-eliza-tlmm-state" 42 additionalProperties: false 43 44$defs: 45 qcom-eliza-tlmm-state: 46 type: object 47 description: 48 Pinctrl node's client devices use subnodes for desired pin configuration. 49 Client device subnodes use below standard properties. 50 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 51 unevaluatedProperties: false 52 53 properties: 54 pins: 55 description: 56 List of gpio pins affected by the properties specified in this 57 subnode. 58 items: 59 oneOf: 60 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$" 61 - enum: [ ufs_reset ] 62 minItems: 1 63 maxItems: 36 64 65 function: 66 description: 67 Specify the alternative function to be configured for the specified 68 pins. 69 enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, 70 audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, 71 cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx, 72 coex_uart2_rx, coex_uart2_tx, dbg_out_clk, 73 ddr_bist_complete, ddr_bist_fail, ddr_bist_start, 74 ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio, 75 gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, 76 hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1, 77 hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec, 78 host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, 79 ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out, 80 mdp_vsync, mdp_vsync0_out, mdp_vsync11_out, 81 mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, 82 mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, 83 pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, 84 pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, 85 prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk, 86 qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, 87 qlink_big_request, qlink_little_enable, 88 qlink_little_request, qlink_wmss, qspi0, qspi_clk, 89 qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, 90 qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, 91 qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, 92 qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, 93 sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, 94 tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, 95 tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, 96 uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, 97 uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, 98 vsense_trigger_mirnat, wcn_sw_ctrl ] 99 required: 100 - pins 101 102required: 103 - compatible 104 - reg 105 106unevaluatedProperties: false 107 108examples: 109 - | 110 #include <dt-bindings/interrupt-controller/arm-gic.h> 111 112 tlmm: pinctrl@f100000 { 113 compatible = "qcom,eliza-tlmm"; 114 reg = <0x0f100000 0x300000>; 115 116 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 117 118 gpio-controller; 119 #gpio-cells = <2>; 120 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 124 gpio-ranges = <&tlmm 0 0 186>; 125 126 gpio-wo-state { 127 pins = "gpio1"; 128 function = "gpio"; 129 }; 130 131 qup-uart14-default-state { 132 pins = "gpio18", "gpio19"; 133 function = "qup2_se5"; 134 drive-strength = <2>; 135 bias-disable; 136 }; 137 }; 138... 139