1*9323f8a0SPrathamesh Shete# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*9323f8a0SPrathamesh Shete%YAML 1.2 3*9323f8a0SPrathamesh Shete--- 4*9323f8a0SPrathamesh Shete$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml# 5*9323f8a0SPrathamesh Shete$schema: http://devicetree.org/meta-schemas/core.yaml# 6*9323f8a0SPrathamesh Shete 7*9323f8a0SPrathamesh Shetetitle: NVIDIA Tegra238 Pinmux Controller 8*9323f8a0SPrathamesh Shete 9*9323f8a0SPrathamesh Shetemaintainers: 10*9323f8a0SPrathamesh Shete - Thierry Reding <thierry.reding@gmail.com> 11*9323f8a0SPrathamesh Shete - Jon Hunter <jonathanh@nvidia.com> 12*9323f8a0SPrathamesh Shete 13*9323f8a0SPrathamesh Shete$ref: nvidia,tegra-pinmux-common.yaml 14*9323f8a0SPrathamesh Shete 15*9323f8a0SPrathamesh Sheteproperties: 16*9323f8a0SPrathamesh Shete nvidia,function: 17*9323f8a0SPrathamesh Shete enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat, 18*9323f8a0SPrathamesh Shete i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0, 19*9323f8a0SPrathamesh Shete usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din, 20*9323f8a0SPrathamesh Shete spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout, 21*9323f8a0SPrathamesh Shete gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat, 22*9323f8a0SPrathamesh Shete i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat, 23*9323f8a0SPrathamesh Shete dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd, 24*9323f8a0SPrathamesh Shete i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd, 25*9323f8a0SPrathamesh Shete uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk, 26*9323f8a0SPrathamesh Shete i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk, 27*9323f8a0SPrathamesh Shete i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk, 28*9323f8a0SPrathamesh Shete i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk, 29*9323f8a0SPrathamesh Shete i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out, 30*9323f8a0SPrathamesh Shete pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l, 31*9323f8a0SPrathamesh Shete pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l, 32*9323f8a0SPrathamesh Shete dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n, 33*9323f8a0SPrathamesh Shete uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk, 34*9323f8a0SPrathamesh Shete sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, 35*9323f8a0SPrathamesh Shete sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec, 36*9323f8a0SPrathamesh Shete gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk, 37*9323f8a0SPrathamesh Shete spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din, 38*9323f8a0SPrathamesh Shete ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0, 39*9323f8a0SPrathamesh Shete ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd, 40*9323f8a0SPrathamesh Shete uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7, 41*9323f8a0SPrathamesh Shete gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat, 42*9323f8a0SPrathamesh Shete rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8, 43*9323f8a0SPrathamesh Shete nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux, 44*9323f8a0SPrathamesh Shete dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat, 45*9323f8a0SPrathamesh Shete dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk, 46*9323f8a0SPrathamesh Shete i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in, 47*9323f8a0SPrathamesh Shete sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk, 48*9323f8a0SPrathamesh Shete ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n, 49*9323f8a0SPrathamesh Shete ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso, 50*9323f8a0SPrathamesh Shete spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0, 51*9323f8a0SPrathamesh Shete spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat, 52*9323f8a0SPrathamesh Shete dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3, 53*9323f8a0SPrathamesh Shete tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3, 54*9323f8a0SPrathamesh Shete sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b, 55*9323f8a0SPrathamesh Shete tsc_edge_out0c, soc_therm_oc2 ] 56*9323f8a0SPrathamesh Shete 57*9323f8a0SPrathamesh Shete # out of the common properties, only these are allowed for Tegra238 58*9323f8a0SPrathamesh Shete nvidia,pins: true 59*9323f8a0SPrathamesh Shete nvidia,pull: true 60*9323f8a0SPrathamesh Shete nvidia,tristate: true 61*9323f8a0SPrathamesh Shete nvidia,schmitt: true 62*9323f8a0SPrathamesh Shete nvidia,enable-input: true 63*9323f8a0SPrathamesh Shete nvidia,open-drain: true 64*9323f8a0SPrathamesh Shete nvidia,lock: true 65*9323f8a0SPrathamesh Shete nvidia,drive-type: true 66*9323f8a0SPrathamesh Shete nvidia,io-hv: true 67*9323f8a0SPrathamesh Shete 68*9323f8a0SPrathamesh Sheterequired: 69*9323f8a0SPrathamesh Shete - nvidia,pins 70*9323f8a0SPrathamesh Shete 71*9323f8a0SPrathamesh SheteadditionalProperties: false 72*9323f8a0SPrathamesh Shete 73*9323f8a0SPrathamesh Shete... 74