1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra238 Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13$ref: nvidia,tegra-pinmux-common.yaml 14 15properties: 16 nvidia,function: 17 enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat, 18 i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0, 19 usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din, 20 spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout, 21 gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat, 22 i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat, 23 dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd, 24 i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd, 25 uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk, 26 i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk, 27 i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk, 28 i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk, 29 i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out, 30 pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l, 31 pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l, 32 dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n, 33 uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk, 34 sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, 35 sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec, 36 gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk, 37 spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din, 38 ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0, 39 ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd, 40 uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7, 41 gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat, 42 rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8, 43 nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux, 44 dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat, 45 dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk, 46 i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in, 47 sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk, 48 ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n, 49 ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso, 50 spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0, 51 spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat, 52 dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3, 53 tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3, 54 sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b, 55 tsc_edge_out0c, soc_therm_oc2 ] 56 57 # out of the common properties, only these are allowed for Tegra238 58 nvidia,pins: true 59 nvidia,pull: true 60 nvidia,tristate: true 61 nvidia,schmitt: true 62 nvidia,enable-input: true 63 nvidia,open-drain: true 64 nvidia,lock: true 65 nvidia,drive-type: true 66 nvidia,io-hv: true 67 68required: 69 - nvidia,pins 70 71additionalProperties: false 72 73... 74