xref: /linux/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 UPHY Pinmux Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  compatible:
15    const: nvidia,tegra264-pinmux-uphy
16
17  reg:
18    maxItems: 1
19
20patternProperties:
21  "^pinmux(-[a-z0-9-]+)?$":
22    type: object
23
24    # pin groups
25    additionalProperties:
26      $ref: nvidia,tegra264-pinmux-common.yaml
27
28      properties:
29        nvidia,pins:
30          items:
31            enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,
32                    pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,
33                    eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,
34                    eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,
35                    pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,
36                    pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,
37                    sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,
38                    soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,
39                    ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,
40                    drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,
41                    drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,
42                    drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,
43                    drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,
44                    drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,
45                    drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,
46                    drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,
47                    drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,
48                    drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,
49                    drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,
50                    drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,
51                    drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]
52
53required:
54  - compatible
55  - reg
56
57additionalProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
62
63    pinmux@82e0000 {
64        compatible = "nvidia,tegra264-pinmux-uphy";
65        reg = <0x82e0000 0x4000>;
66
67        pinctrl-names = "default";
68        pinctrl-0 = <&pinmux_default>;
69
70        pinmux_default: pinmux-default {
71            pex {
72                nvidia,pins = "pex_l1_rst_n_pb1";
73                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74                nvidia,tristate = <TEGRA_PIN_DISABLE>;
75                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76            };
77        };
78    };
79