xref: /linux/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml (revision 53c7db5c1916afcecc8683ae01ff8415c708a883) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra264 AON Pinmux Controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  compatible:
15    const: nvidia,tegra264-pinmux-aon
16
17  reg:
18    maxItems: 1
19
20patternProperties:
21  "^pinmux(-[a-z0-9-]+)?$":
22    type: object
23
24    # pin groups
25    additionalProperties:
26      $ref: nvidia,tegra264-pinmux-common.yaml
27
28      properties:
29        nvidia,pins:
30          items:
31            enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
32                    batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
33                    hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
34                    soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
35                    gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
36                    uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
37                    spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
38                    soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
39                    soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
40                    soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
41                    drive_ao_retention_n_paa2, drive_batt_oc_paa3,
42                    drive_power_on_paa5, drive_vcomp_alert_paa1,
43                    drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
44                    drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
45                    drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
46                    drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
47                    drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
48                    drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
49                    drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
50                    drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
51                    drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
52                    drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
53                    drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
54                    drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
55                    drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
56
57required:
58  - compatible
59  - reg
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
66
67    pinmux@c7a2000 {
68        compatible = "nvidia,tegra264-pinmux-aon";
69        reg = <0xc7a2000 0x2000>;
70
71        pinctrl-names = "default";
72        pinctrl-0 = <&state_default>;
73
74        state_default: pinmux-default {
75            uart0 {
76                nvidia,pins = "uart0_tx_pcc5";
77                nvidia,function = "uarta_txd";
78            };
79        };
80    };
81