1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra238 AON Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 const: nvidia,tegra238-pinmux-aon 16 17 reg: 18 maxItems: 1 19 20patternProperties: 21 "^pinmux(-[a-z0-9-]+)?$": 22 type: object 23 24 # pin groups 25 additionalProperties: 26 $ref: nvidia,tegra238-pinmux-common.yaml 27 28 properties: 29 nvidia,pins: 30 items: 31 enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, 32 pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, 33 soc_gpio25_paa6, soc_gpio26_paa7, 34 hdmi_cec_pbb0, 35 spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, 36 spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, 37 uart3_rx_pcc6, gen2_i2c_scl_pcc7, 38 gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, 39 gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, 40 dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, 41 pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, 42 soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, 43 soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, 44 soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, 45 soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, 46 soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, 47 uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, 48 uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, 49 uart5_cts_phh2, soc_gpio86_phh3, 50 # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) 51 drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, 52 drive_vcomp_alert_paa2, drive_pwm1_paa3, 53 drive_batt_oc_paa4, drive_soc_gpio04_paa5, 54 drive_soc_gpio25_paa6, drive_soc_gpio26_paa7, 55 drive_hdmi_cec_pbb0, 56 drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, 57 drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3, 58 drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5, 59 drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7, 60 drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1, 61 drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, 62 drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, 63 drive_soc_gpio19_pdd6, drive_pwm2_pdd7, 64 drive_pwm3_pee0, drive_pwm7_pee1, 65 drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, 66 drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, 67 drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, 68 drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, 69 drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, 70 drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, 71 drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, 72 drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, 73 drive_uart5_tx_pgg7, drive_uart5_rx_phh0, 74 drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, 75 drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, 76 drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] 77 78required: 79 - compatible 80 - reg 81 82additionalProperties: false 83 84examples: 85 - | 86 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 87 88 pinmux@c300000 { 89 compatible = "nvidia,tegra238-pinmux-aon"; 90 reg = <0x0c300000 0x4000>; 91 92 pinctrl-names = "cec"; 93 pinctrl-0 = <&cec_state>; 94 95 cec_state: pinmux-cec { 96 cec { 97 nvidia,pins = "hdmi_cec_pbb0"; 98 nvidia,function = "hdmi_cec"; 99 }; 100 }; 101 }; 102... 103