1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Spacemit K3 PCIE/USB3 Comb PHY 8 9maintainers: 10 - Inochi Amaoto <inochiama@gmail.com> 11 12properties: 13 compatible: 14 const: spacemit,k3-combo-phy 15 16 reg: 17 maxItems: 1 18 19 "#phy-cells": 20 const: 2 21 description: 22 The first one is phy id, the second one is phy type. This 23 only supports types are PCIe and USB . 24 25 spacemit,apb-spare: 26 $ref: /schemas/types.yaml#/definitions/phandle 27 description: 28 Phandle to APB SPARE system controller interface, used for 29 PHY calibration. 30 31 spacemit,apmu: 32 $ref: /schemas/types.yaml#/definitions/phandle-array 33 items: 34 - items: 35 - description: phandle of APMU syscon 36 - description: configuration of the PHY lanes 37 description: | 38 Phandle to control PHY mux configuration. The configuration 39 is described as follows: 40 bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode 41 bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode 42 bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode 43 bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode 44 bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode 45 46 The bit[3:0] is only valid when bit 4 is 1. 47 48 This mux control does not affect the PHY for PCIe E, it is always 49 in PCIe mode. 50 51required: 52 - compatible 53 - reg 54 - "#phy-cells" 55 - spacemit,apb-spare 56 - spacemit,apmu 57 58additionalProperties: false 59 60examples: 61 - | 62 phy@81d00000 { 63 compatible = "spacemit,k3-combo-phy"; 64 reg = <0x81d00000 0x600000>; 65 #phy-cells = <2>; 66 spacemit,apb-spare = <&apb_spare>; 67 spacemit,apmu = <&apmu 0x00>; 68 }; 69