1*4f816512SBiju Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4f816512SBiju Das%YAML 1.2 3*4f816512SBiju Das--- 4*4f816512SBiju Das$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml# 5*4f816512SBiju Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4f816512SBiju Das 7*4f816512SBiju Dastitle: Renesas RZ/G3E USB 3.0 PHY 8*4f816512SBiju Das 9*4f816512SBiju Dasmaintainers: 10*4f816512SBiju Das - Biju Das <biju.das.jz@bp.renesas.com> 11*4f816512SBiju Das 12*4f816512SBiju Dasproperties: 13*4f816512SBiju Das compatible: 14*4f816512SBiju Das const: renesas,r9a09g047-usb3-phy 15*4f816512SBiju Das 16*4f816512SBiju Das reg: 17*4f816512SBiju Das maxItems: 1 18*4f816512SBiju Das 19*4f816512SBiju Das clocks: 20*4f816512SBiju Das items: 21*4f816512SBiju Das - description: APB bus clock 22*4f816512SBiju Das - description: USB 2.0 PHY reference clock 23*4f816512SBiju Das - description: USB 3.0 PHY reference clock 24*4f816512SBiju Das 25*4f816512SBiju Das clock-names: 26*4f816512SBiju Das items: 27*4f816512SBiju Das - const: pclk 28*4f816512SBiju Das - const: core 29*4f816512SBiju Das - const: ref_alt_clk_p 30*4f816512SBiju Das 31*4f816512SBiju Das power-domains: 32*4f816512SBiju Das maxItems: 1 33*4f816512SBiju Das 34*4f816512SBiju Das resets: 35*4f816512SBiju Das maxItems: 1 36*4f816512SBiju Das 37*4f816512SBiju Das '#phy-cells': 38*4f816512SBiju Das const: 0 39*4f816512SBiju Das 40*4f816512SBiju Dasrequired: 41*4f816512SBiju Das - compatible 42*4f816512SBiju Das - reg 43*4f816512SBiju Das - clocks 44*4f816512SBiju Das - clock-names 45*4f816512SBiju Das - power-domains 46*4f816512SBiju Das - resets 47*4f816512SBiju Das - '#phy-cells' 48*4f816512SBiju Das 49*4f816512SBiju DasadditionalProperties: false 50*4f816512SBiju Das 51*4f816512SBiju Dasexamples: 52*4f816512SBiju Das - | 53*4f816512SBiju Das #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 54*4f816512SBiju Das 55*4f816512SBiju Das usb-phy@15870000 { 56*4f816512SBiju Das compatible = "renesas,r9a09g047-usb3-phy"; 57*4f816512SBiju Das reg = <0x15870000 0x10000>; 58*4f816512SBiju Das clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>; 59*4f816512SBiju Das clock-names = "pclk", "core", "ref_alt_clk_p"; 60*4f816512SBiju Das power-domains = <&cpg>; 61*4f816512SBiju Das resets = <&cpg 0xaa>; 62*4f816512SBiju Das #phy-cells = <0>; 63*4f816512SBiju Das }; 64