xref: /linux/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml (revision 0623fdf30b1105c22f58baeeca954c803bdf5f8b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G3E USB 3.0 PHY
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12properties:
13  compatible:
14    const: renesas,r9a09g047-usb3-phy
15
16  reg:
17    maxItems: 1
18
19  clocks:
20    items:
21      - description: APB bus clock
22      - description: USB 2.0 PHY reference clock
23      - description: USB 3.0 PHY reference clock
24
25  clock-names:
26    items:
27      - const: pclk
28      - const: core
29      - const: ref_alt_clk_p
30
31  power-domains:
32    maxItems: 1
33
34  resets:
35    maxItems: 1
36
37  '#phy-cells':
38    const: 0
39
40required:
41  - compatible
42  - reg
43  - clocks
44  - clock-names
45  - power-domains
46  - resets
47  - '#phy-cells'
48
49additionalProperties: false
50
51examples:
52  - |
53    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
54
55    usb-phy@15870000 {
56        compatible = "renesas,r9a09g047-usb3-phy";
57        reg = <0x15870000 0x10000>;
58        clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
59        clock-names = "pclk", "core", "ref_alt_clk_p";
60        power-domains = <&cpg>;
61        resets = <&cpg 0xaa>;
62        #phy-cells = <0>;
63    };
64