1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur) 8 9maintainers: 10 - Qiang Yu <qiang.yu@oss.qualcomm.com> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> 12 13description: | 14 The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the 15 PCIe3a/PCIe3b controllers. This block supports two link modes, selected 16 at runtime via a TCSR syscon register: 17 18 1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only) 19 2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and 20 PCIe3b) 21 22 The node always describes both PHY instances ("port a" and "port b"), 23 regardless of which link mode is active on the board. 24 25properties: 26 compatible: 27 enum: 28 - qcom,glymur-qmp-gen5x8-pcie-phy 29 30 reg: 31 maxItems: 2 32 33 reg-names: 34 items: 35 - const: port_a 36 - const: port_b 37 38 clocks: 39 maxItems: 10 40 41 clock-names: 42 items: 43 - const: aux 44 - const: cfg_ahb 45 - const: ref 46 - const: rchng 47 - const: pipe 48 - const: phy_b_aux 49 - const: cfg_ahb_b 50 - const: rchng_b 51 - const: pipe_b 52 - const: pipediv2_b 53 54 power-domains: 55 maxItems: 2 56 57 power-domain-names: 58 items: 59 - const: port_a 60 - const: port_b 61 62 resets: 63 maxItems: 4 64 65 reset-names: 66 items: 67 - const: port_a 68 - const: port_a_nocsr 69 - const: port_b 70 - const: port_b_nocsr 71 72 vdda-phy-supply: true 73 74 vdda-pll-supply: true 75 76 vdda-refgen0p9-supply: true 77 78 vdda-refgen1p2-supply: true 79 80 qcom,link-mode: 81 description: 82 Reference to a register in the TCSR syscon that reports the link 83 mode the PCIe PHY is currently configured for, either a single x8 84 link or two independent x4 links. The link mode is programmed by 85 firmware before Linux boots; this property is only used to read 86 the active link mode, specified as a phandle to the syscon and 87 the register offset. 88 $ref: /schemas/types.yaml#/definitions/phandle-array 89 items: 90 - items: 91 - description: phandle of TCSR syscon 92 - description: offset of link mode register 93 94 "#clock-cells": 95 const: 1 96 97 clock-output-names: 98 items: 99 - description: Name of the PHY A pipe clock output. 100 - description: Name of the PHY B pipe clock output. 101 102 "#phy-cells": 103 const: 1 104 description: 105 The cell is the index of the sub-PHY within the active link 106 mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in 107 x4x4 mode, and only index 0 (the single wide PHY) is valid in 108 x8 mode. 109 110required: 111 - compatible 112 - reg 113 - reg-names 114 - clocks 115 - clock-names 116 - power-domains 117 - power-domain-names 118 - resets 119 - reset-names 120 - vdda-phy-supply 121 - vdda-pll-supply 122 - vdda-refgen0p9-supply 123 - vdda-refgen1p2-supply 124 - qcom,link-mode 125 - "#clock-cells" 126 - clock-output-names 127 - "#phy-cells" 128 129additionalProperties: false 130 131examples: 132 - | 133 #include <dt-bindings/clock/qcom,glymur-gcc.h> 134 #include <dt-bindings/clock/qcom,glymur-tcsr.h> 135 136 phy@f00000 { 137 compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; 138 reg = <0x00f00000 0x10000>, <0x00f10000 0x10000>; 139 reg-names = "port_a", "port_b"; 140 141 clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, 142 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 143 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 144 <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, 145 <&gcc GCC_PCIE_3A_PIPE_CLK>, 146 <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 147 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 148 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 149 <&gcc GCC_PCIE_3B_PIPE_CLK>, 150 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 151 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 152 "phy_b_aux", "cfg_ahb_b", "rchng_b", "pipe_b", 153 "pipediv2_b"; 154 155 resets = <&gcc GCC_PCIE_3A_PHY_BCR>, 156 <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, 157 <&gcc GCC_PCIE_3B_PHY_BCR>, 158 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 159 reset-names = "port_a", "port_a_nocsr", "port_b", "port_b_nocsr"; 160 161 power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, 162 <&gcc GCC_PCIE_3B_PHY_GDSC>; 163 power-domain-names = "port_a", "port_b"; 164 165 vdda-phy-supply = <&vreg_l3c>; 166 vdda-pll-supply = <&vreg_l2c>; 167 168 vdda-refgen0p9-supply = <&vreg_l3c>; 169 vdda-refgen1p2-supply = <&vreg_l2c>; 170 171 qcom,link-mode = <&tcsr 0x5000>; 172 173 #clock-cells = <1>; 174 clock-output-names = "pcie3a_pipe_clk", "pcie3b_pipe_clk"; 175 176 #phy-cells = <1>; 177 }; 178