xref: /linux/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: StarFive JH8100 StarLink PMU
8
9maintainers:
10  - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
11
12description:
13  StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
14  shared L3 memory system. The PMU support overflow interrupt, up to
15  16 programmable 64bit event counters, and an independent 64bit cycle
16  counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
17
18properties:
19  compatible:
20    const: starfive,jh8100-starlink-pmu
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28required:
29  - compatible
30  - reg
31  - interrupts
32
33additionalProperties: false
34
35examples:
36  - |
37    soc {
38        #address-cells = <2>;
39        #size-cells = <2>;
40
41        pmu@12900000 {
42            compatible = "starfive,jh8100-starlink-pmu";
43            reg = <0x0 0x12900000 0x0 0x10000>;
44            interrupts = <34>;
45        };
46    };
47