xref: /linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml (revision b2128290c29902315e632ea59e0504d6bc9e9b42) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UltraRISC DP1000 PCIe Host Controller
8
9description:
10  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
11
12maintainers:
13  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
14  - Jia Wang <wangjia@ultrarisc.com>
15
16allOf:
17  - $ref: /schemas/pci/snps,dw-pcie.yaml#
18
19properties:
20  compatible:
21    const: ultrarisc,dp1000-pcie
22
23  reg:
24    items:
25      - description: Data Bus Interface (DBI) registers.
26      - description: PCIe configuration space region.
27
28  reg-names:
29    items:
30      - const: dbi
31      - const: config
32
33  num-lanes:
34    $ref: /schemas/types.yaml#/definitions/uint32
35    enum: [4, 16]
36    description: Number of lanes to use.
37
38  interrupts:
39    items:
40      - description: MSI interrupt
41      - description: Legacy INTA interrupt
42      - description: Legacy INTB interrupt
43      - description: Legacy INTC interrupt
44      - description: Legacy INTD interrupt
45
46  interrupt-names:
47    items:
48      - const: msi
49      - const: inta
50      - const: intb
51      - const: intc
52      - const: intd
53
54required:
55  - compatible
56  - reg
57  - reg-names
58  - interrupts
59  - interrupt-names
60
61unevaluatedProperties: false
62
63examples:
64  - |
65    soc {
66      #address-cells = <2>;
67      #size-cells = <2>;
68
69      pcie@21000000 {
70        compatible = "ultrarisc,dp1000-pcie";
71        reg = <0x0 0x21000000 0x0 0x01000000>,
72              <0x0 0x4fff0000 0x0 0x00010000>;
73        reg-names = "dbi", "config";
74        ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
75                 <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
76                 <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
77        #address-cells = <3>;
78        #size-cells = <2>;
79        #interrupt-cells = <1>;
80        device_type = "pci";
81        dma-coherent;
82        bus-range = <0x0 0xff>;
83        num-lanes = <16>;
84        interrupt-parent = <&plic>;
85        interrupts = <43>, <44>, <45>, <46>, <47>;
86        interrupt-names = "msi", "inta", "intb", "intc", "intd";
87        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
88        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
89                        <0x0 0x0 0x0 0x2 &plic 45>,
90                        <0x0 0x0 0x0 0x3 &plic 46>,
91                        <0x0 0x0 0x0 0x4 &plic 47>;
92      };
93    };
94