xref: /linux/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml (revision 3216ceeb708b816ffacb19ae2387ac68bb872631) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: DesignWare based PCIe controller on Rockchip SoCs
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11  - Simon Xue <xxm@rock-chips.com>
12  - Heiko Stuebner <heiko@sntech.de>
13
14description: |+
15  RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16  PCIe IP and thus inherits all the common properties defined in
17  snps,dw-pcie.yaml.
18
19allOf:
20  - $ref: /schemas/pci/snps,dw-pcie.yaml#
21
22properties:
23  compatible:
24    oneOf:
25      - const: rockchip,rk3568-pcie
26      - items:
27          - enum:
28              - rockchip,rk3588-pcie
29          - const: rockchip,rk3568-pcie
30
31  reg:
32    items:
33      - description: Data Bus Interface (DBI) registers
34      - description: Rockchip designed configuration registers
35      - description: Config registers
36
37  reg-names:
38    items:
39      - const: dbi
40      - const: apb
41      - const: config
42
43  clocks:
44    minItems: 5
45    items:
46      - description: AHB clock for PCIe master
47      - description: AHB clock for PCIe slave
48      - description: AHB clock for PCIe dbi
49      - description: APB clock for PCIe
50      - description: Auxiliary clock for PCIe
51      - description: PIPE clock
52
53  clock-names:
54    minItems: 5
55    items:
56      - const: aclk_mst
57      - const: aclk_slv
58      - const: aclk_dbi
59      - const: pclk
60      - const: aux
61      - const: pipe
62
63  msi-map: true
64
65  num-lanes: true
66
67  phys:
68    maxItems: 1
69
70  phy-names:
71    const: pcie-phy
72
73  power-domains:
74    maxItems: 1
75
76  ranges:
77    minItems: 2
78    maxItems: 3
79
80  resets:
81    minItems: 1
82    maxItems: 2
83
84  reset-names:
85    oneOf:
86      - const: pipe
87      - items:
88          - const: pwr
89          - const: pipe
90
91  vpcie3v3-supply: true
92
93required:
94  - compatible
95  - reg
96  - reg-names
97  - clocks
98  - clock-names
99  - msi-map
100  - num-lanes
101  - phys
102  - phy-names
103  - power-domains
104  - resets
105  - reset-names
106
107unevaluatedProperties: false
108
109examples:
110  - |
111
112    bus {
113        #address-cells = <2>;
114        #size-cells = <2>;
115
116        pcie3x2: pcie@fe280000 {
117            compatible = "rockchip,rk3568-pcie";
118            reg = <0x3 0xc0800000 0x0 0x390000>,
119                  <0x0 0xfe280000 0x0 0x10000>,
120                  <0x3 0x80000000 0x0 0x100000>;
121            reg-names = "dbi", "apb", "config";
122            bus-range = <0x20 0x2f>;
123            clocks = <&cru 143>, <&cru 144>,
124                     <&cru 145>, <&cru 146>,
125                     <&cru 147>;
126            clock-names = "aclk_mst", "aclk_slv",
127                          "aclk_dbi", "pclk",
128                          "aux";
129            device_type = "pci";
130            linux,pci-domain = <2>;
131            max-link-speed = <2>;
132            msi-map = <0x2000 &its 0x2000 0x1000>;
133            num-lanes = <2>;
134            phys = <&pcie30phy>;
135            phy-names = "pcie-phy";
136            power-domains = <&power 15>;
137            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
138                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
139            resets = <&cru 193>;
140            reset-names = "pipe";
141            #address-cells = <3>;
142            #size-cells = <2>;
143        };
144    };
145...
146