1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/G3S PCIe host controller 8 9maintainers: 10 - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> 11 12description: 13 Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification 14 4.0 and supports up to 5 GT/s (Gen2). 15 16properties: 17 compatible: 18 const: renesas,r9a08g045-pcie # RZ/G3S 19 20 reg: 21 maxItems: 1 22 23 interrupts: 24 items: 25 - description: System error interrupt 26 - description: System error on correctable error interrupt 27 - description: System error on non-fatal error interrupt 28 - description: System error on fatal error interrupt 29 - description: AXI error interrupt 30 - description: INTA interrupt 31 - description: INTB interrupt 32 - description: INTC interrupt 33 - description: INTD interrupt 34 - description: MSI interrupt 35 - description: Link bandwidth interrupt 36 - description: PME interrupt 37 - description: DMA interrupt 38 - description: PCIe event interrupt 39 - description: Message interrupt 40 - description: All interrupts 41 42 interrupt-names: 43 items: 44 - description: serr 45 - description: ser_cor 46 - description: serr_nonfatal 47 - description: serr_fatal 48 - description: axi_err 49 - description: inta 50 - description: intb 51 - description: intc 52 - description: intd 53 - description: msi 54 - description: link_bandwidth 55 - description: pm_pme 56 - description: dma 57 - description: pcie_evt 58 - description: msg 59 - description: all 60 61 interrupt-controller: true 62 63 clocks: 64 items: 65 - description: System clock 66 - description: PM control clock 67 68 clock-names: 69 items: 70 - description: aclk 71 - description: pm 72 73 resets: 74 items: 75 - description: AXI2PCIe Bridge reset 76 - description: Data link layer/transaction layer reset 77 - description: Transaction layer (ACLK domain) reset 78 - description: Transaction layer (PCLK domain) reset 79 - description: Physical layer reset 80 - description: Configuration register reset 81 - description: Configuration register reset 82 83 reset-names: 84 items: 85 - description: aresetn 86 - description: rst_b 87 - description: rst_gp_b 88 - description: rst_ps_b 89 - description: rst_rsm_b 90 - description: rst_cfg_b 91 - description: rst_load_b 92 93 power-domains: 94 maxItems: 1 95 96 dma-ranges: 97 description: 98 A single range for the inbound memory region. 99 maxItems: 1 100 101 renesas,sysc: 102 description: | 103 System controller registers control and monitor various PCIe 104 functionalities. 105 106 Control: 107 - transition to L1 state 108 - receiver termination settings 109 - RST_RSM_B signal 110 111 Monitor: 112 - clkl1pm clock request state 113 - power off information in L2 state 114 - errors (fatal, non-fatal, correctable) 115 $ref: /schemas/types.yaml#/definitions/phandle 116 117patternProperties: 118 "^pcie@0,[0-0]$": 119 type: object 120 allOf: 121 - $ref: /schemas/pci/pci-pci-bridge.yaml# 122 123 properties: 124 reg: 125 maxItems: 1 126 127 vendor-id: 128 const: 0x1912 129 130 device-id: 131 const: 0x0033 132 133 clocks: 134 items: 135 - description: Reference clock 136 137 clock-names: 138 items: 139 - const: ref 140 141 required: 142 - device_type 143 - vendor-id 144 - device-id 145 - clocks 146 - clock-names 147 148 unevaluatedProperties: false 149 150required: 151 - compatible 152 - reg 153 - clocks 154 - clock-names 155 - resets 156 - reset-names 157 - interrupts 158 - interrupt-names 159 - interrupt-map 160 - interrupt-map-mask 161 - interrupt-controller 162 - power-domains 163 - "#address-cells" 164 - "#size-cells" 165 - "#interrupt-cells" 166 - renesas,sysc 167 168allOf: 169 - $ref: /schemas/pci/pci-host-bridge.yaml# 170 171unevaluatedProperties: false 172 173examples: 174 - | 175 #include <dt-bindings/clock/r9a08g045-cpg.h> 176 #include <dt-bindings/interrupt-controller/arm-gic.h> 177 178 bus { 179 #address-cells = <2>; 180 #size-cells = <2>; 181 182 pcie@11e40000 { 183 compatible = "renesas,r9a08g045-pcie"; 184 reg = <0 0x11e40000 0 0x10000>; 185 ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; 186 /* Map all possible DRAM ranges (4 GB). */ 187 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; 188 bus-range = <0x0 0xff>; 189 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-names = "serr", "serr_cor", "serr_nonfatal", 206 "serr_fatal", "axi_err", "inta", 207 "intb", "intc", "intd", "msi", 208 "link_bandwidth", "pm_pme", "dma", 209 "pcie_evt", "msg", "all"; 210 #interrupt-cells = <1>; 211 interrupt-controller; 212 interrupt-map-mask = <0 0 0 7>; 213 interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ 214 <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ 215 <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ 216 <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ 217 clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, 218 <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; 219 clock-names = "aclk", "pm"; 220 resets = <&cpg R9A08G045_PCI_ARESETN>, 221 <&cpg R9A08G045_PCI_RST_B>, 222 <&cpg R9A08G045_PCI_RST_GP_B>, 223 <&cpg R9A08G045_PCI_RST_PS_B>, 224 <&cpg R9A08G045_PCI_RST_RSM_B>, 225 <&cpg R9A08G045_PCI_RST_CFG_B>, 226 <&cpg R9A08G045_PCI_RST_LOAD_B>; 227 reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", 228 "rst_rsm_b", "rst_cfg_b", "rst_load_b"; 229 power-domains = <&cpg>; 230 device_type = "pci"; 231 #address-cells = <3>; 232 #size-cells = <2>; 233 renesas,sysc = <&sysc>; 234 235 pcie@0,0 { 236 reg = <0x0 0x0 0x0 0x0 0x0>; 237 ranges; 238 clocks = <&versa3 5>; 239 clock-names = "ref"; 240 device_type = "pci"; 241 vendor-id = <0x1912>; 242 device-id = <0x0033>; 243 #address-cells = <3>; 244 #size-cells = <2>; 245 }; 246 }; 247 }; 248 249... 250