xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq9574.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ9574 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

properties:
  compatible:
    oneOf:
      - enum:
          - qcom,pcie-ipq9574
      - items:
          - enum:
              - qcom,pcie-ipq5332
              - qcom,pcie-ipq5424
          - const: qcom,pcie-ipq9574

  reg:
    maxItems: 6

  reg-names:
    items:
      - const: dbi
      - const: elbi
      - const: atu
      - const: parf
      - const: config
      - const: mhi

  clocks:
    maxItems: 6

  clock-names:
    items:
      - const: axi_m # AXI Master clock
      - const: axi_s # AXI Slave clock
      - const: axi_bridge
      - const: rchng
      - const: ahb
      - const: aux

  interrupts:
    minItems: 8
    maxItems: 9

  interrupt-names:
    minItems: 8
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    maxItems: 8

  reset-names:
    items:
      - const: pipe
      - const: sticky # Core sticky reset
      - const: axi_s_sticky # AXI Slave Sticky reset
      - const: axi_s # AXI slave reset
      - const: axi_m_sticky # AXI Master Sticky reset
      - const: axi_m # AXI master reset
      - const: aux
      - const: ahb

required:
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interconnect/qcom,ipq9574.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>

    pcie@10000000 {
        compatible = "qcom,pcie-ipq9574";
        reg = <0x10000000 0xf1d>,
              <0x10000f20 0xa8>,
              <0x10001000 0x1000>,
              <0x000f8000 0x4000>,
              <0x10100000 0x1000>,
              <0x000fe000 0x1000>;
        reg-names = "dbi",
                "elbi",
                "atu",
                "parf",
                "config",
                "mhi";
        ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
                 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;

        device_type = "pci";
        linux,pci-domain = <1>;
        bus-range = <0x00 0xff>;
        num-lanes = <1>;
        #address-cells = <3>;
        #size-cells = <2>;

        clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
                 <&gcc GCC_PCIE1_AXI_S_CLK>,
                 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
                 <&gcc GCC_PCIE1_RCHNG_CLK>,
                 <&gcc GCC_PCIE1_AHB_CLK>,
                 <&gcc GCC_PCIE1_AUX_CLK>;
        clock-names = "axi_m",
                      "axi_s",
                      "axi_bridge",
                      "rchng",
                      "ahb",
                      "aux";

        interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
                        <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
        interconnect-names = "pcie-mem", "cpu-pcie";

        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi0",
                          "msi1",
                          "msi2",
                          "msi3",
                          "msi4",
                          "msi5",
                          "msi6",
                          "msi7";

        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

        resets = <&gcc GCC_PCIE1_PIPE_ARES>,
                 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
                 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
                 <&gcc GCC_PCIE1_AXI_S_ARES>,
                 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
                 <&gcc GCC_PCIE1_AXI_M_ARES>,
                 <&gcc GCC_PCIE1_AUX_ARES>,
                 <&gcc GCC_PCIE1_AHB_ARES>;
        reset-names = "pipe",
                      "sticky",
                      "axi_s_sticky",
                      "axi_s",
                      "axi_m_sticky",
                      "axi_m",
                      "aux",
                      "ahb";

        phys = <&pcie1_phy>;
        phy-names = "pciephy";

        perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
        wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
    };