xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq9574.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm IPQ9574 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - qcom,pcie-ipq9574
18      - items:
19          - enum:
20              - qcom,pcie-ipq5332
21              - qcom,pcie-ipq5424
22          - const: qcom,pcie-ipq9574
23
24  reg:
25    maxItems: 6
26
27  reg-names:
28    items:
29      - const: dbi
30      - const: elbi
31      - const: atu
32      - const: parf
33      - const: config
34      - const: mhi
35
36  clocks:
37    maxItems: 6
38
39  clock-names:
40    items:
41      - const: axi_m # AXI Master clock
42      - const: axi_s # AXI Slave clock
43      - const: axi_bridge
44      - const: rchng
45      - const: ahb
46      - const: aux
47
48  interrupts:
49    minItems: 8
50    maxItems: 9
51
52  interrupt-names:
53    minItems: 8
54    items:
55      - const: msi0
56      - const: msi1
57      - const: msi2
58      - const: msi3
59      - const: msi4
60      - const: msi5
61      - const: msi6
62      - const: msi7
63      - const: global
64
65  resets:
66    maxItems: 8
67
68  reset-names:
69    items:
70      - const: pipe
71      - const: sticky # Core sticky reset
72      - const: axi_s_sticky # AXI Slave Sticky reset
73      - const: axi_s # AXI slave reset
74      - const: axi_m_sticky # AXI Master Sticky reset
75      - const: axi_m # AXI master reset
76      - const: aux
77      - const: ahb
78
79required:
80  - resets
81  - reset-names
82
83allOf:
84  - $ref: qcom,pcie-common.yaml#
85
86unevaluatedProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
91    #include <dt-bindings/gpio/gpio.h>
92    #include <dt-bindings/interconnect/qcom,ipq9574.h>
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
95
96    pcie@10000000 {
97        compatible = "qcom,pcie-ipq9574";
98        reg = <0x10000000 0xf1d>,
99              <0x10000f20 0xa8>,
100              <0x10001000 0x1000>,
101              <0x000f8000 0x4000>,
102              <0x10100000 0x1000>,
103              <0x000fe000 0x1000>;
104        reg-names = "dbi",
105                "elbi",
106                "atu",
107                "parf",
108                "config",
109                "mhi";
110        ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
111                 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
112
113        device_type = "pci";
114        linux,pci-domain = <1>;
115        bus-range = <0x00 0xff>;
116        num-lanes = <1>;
117        #address-cells = <3>;
118        #size-cells = <2>;
119
120        clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
121                 <&gcc GCC_PCIE1_AXI_S_CLK>,
122                 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
123                 <&gcc GCC_PCIE1_RCHNG_CLK>,
124                 <&gcc GCC_PCIE1_AHB_CLK>,
125                 <&gcc GCC_PCIE1_AUX_CLK>;
126        clock-names = "axi_m",
127                      "axi_s",
128                      "axi_bridge",
129                      "rchng",
130                      "ahb",
131                      "aux";
132
133        interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
134                        <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
135        interconnect-names = "pcie-mem", "cpu-pcie";
136
137        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
138                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
139                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
140                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
141                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
142                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
143                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
144                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
145        interrupt-names = "msi0",
146                          "msi1",
147                          "msi2",
148                          "msi3",
149                          "msi4",
150                          "msi5",
151                          "msi6",
152                          "msi7";
153
154        #interrupt-cells = <1>;
155        interrupt-map-mask = <0 0 0 0x7>;
156        interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
157                        <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
158                        <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
159                        <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
160
161        resets = <&gcc GCC_PCIE1_PIPE_ARES>,
162                 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
163                 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
164                 <&gcc GCC_PCIE1_AXI_S_ARES>,
165                 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
166                 <&gcc GCC_PCIE1_AXI_M_ARES>,
167                 <&gcc GCC_PCIE1_AUX_ARES>,
168                 <&gcc GCC_PCIE1_AHB_ARES>;
169        reset-names = "pipe",
170                      "sticky",
171                      "axi_s_sticky",
172                      "axi_s",
173                      "axi_m_sticky",
174                      "axi_m",
175                      "aux",
176                      "ahb";
177
178        phys = <&pcie1_phy>;
179        phy-names = "pciephy";
180
181        perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
182        wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
183    };
184