xref: /linux/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml (revision 570f7e331f5febb30f1384817463c7e42b65ca7d)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Hawi PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

description:
  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
  the Synopsys DesignWare PCIe IP.

properties:
  compatible:
    oneOf:
      - const: qcom,hawi-pcie
      - items:
          - enum:
              - qcom,maili-pcie
          - const: qcom,hawi-pcie

  reg:
    items:
      - description: Qualcomm specific registers
      - description: DesignWare PCIe registers
      - description: External local bus interface registers
      - description: ATU address space
      - description: PCIe configuration space
      - description: MHI registers

  reg-names:
    items:
      - const: parf
      - const: dbi
      - const: elbi
      - const: atu
      - const: config
      - const: mhi

  clocks:
    items:
      - description: PCIe Auxiliary clock
      - description: PCIe Configuration clock
      - description: PCIe Master AXI clock
      - description: PCIe Slave AXI clock
      - description: PCIe Slave Q2A AXI clock
      - description: PCIe Aggre NoC AXI clock
      - description: PCIe Config NoC AXI clock

  clock-names:
    items:
      - const: aux
      - const: cfg
      - const: bus_master
      - const: bus_slave
      - const: slave_q2a
      - const: noc_aggr
      - const: cnoc_sf_axi

  interrupts:
    minItems: 9
    maxItems: 9

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    items:
      - description: PCIe core reset
      - description: PCIe link down reset

  reset-names:
    items:
      - const: pci
      - const: link_down

required:
  - power-domains
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@1c00000 {
            compatible = "qcom,hawi-pcie";
            reg = <0 0x01c00000 0 0x3000>,
                  <0 0x40000000 0 0xf1d>,
                  <0 0x40000f20 0 0xa8>,
                  <0 0x40001000 0 0x1000>,
                  <0 0x40100000 0 0x100000>,
                  <0 0x01c03000 0 0x1000>;
            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;

            bus-range = <0x00 0xff>;
            device_type = "pci";
            linux,pci-domain = <0>;
            num-lanes = <2>;

            #address-cells = <3>;
            #size-cells = <2>;

            clocks = <&gcc_pcie_0_aux_clk>,
                     <&gcc_pcie_0_cfg_ahb_clk>,
                     <&gcc_pcie_0_mstr_axi_clk>,
                     <&gcc_pcie_0_slv_axi_clk>,
                     <&gcc_pcie_0_slv_q2a_axi_clk>,
                     <&gcc_aggre_noc_pcie_axi_clk>,
                     <&gcc_cnoc_pcie_sf_axi_clk>;
            clock-names = "aux",
                          "cfg",
                          "bus_master",
                          "bus_slave",
                          "slave_q2a",
                          "noc_aggr",
                          "cnoc_sf_axi";

            dma-coherent;

            interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0", "msi1", "msi2", "msi3",
                              "msi4", "msi5", "msi6", "msi7", "global";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                            <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                            <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                            <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

            interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS
                             &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
                            <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
                             &cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
            interconnect-names = "pcie-mem", "cpu-pcie";

            iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
                        <0x100 &apps_smmu 0x1001 0x1>;

            pinctrl-0 = <&pcie0_default_state>;
            pinctrl-names = "default";

            power-domains = <&gcc_pcie_0_phy_gdsc>;

            resets = <&gcc_pcie_0_bcr>,
                     <&gcc_pcie_0_link_down_bcr>;
            reset-names = "pci", "link_down";

            msi-map = <0x0 &gic_its 0x1000 0x1>,
                      <0x100 &gic_its 0x1001 0x1>;
            msi-map-mask = <0xff00>;

            pcie@0 {
                device_type = "pci";
                reg = <0x0 0x0 0x0 0x0 0x0>;
                bus-range = <0x01 0xff>;

                #address-cells = <3>;
                #size-cells = <2>;
                ranges;

                phys = <&pcie0_phy>;
                wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
                reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
            };
        };
    };