1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Hawi PCI Express Root Complex 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Manivannan Sadhasivam <mani@kernel.org> 12 13description: 14 Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on 15 the Synopsys DesignWare PCIe IP. 16 17properties: 18 compatible: 19 oneOf: 20 - const: qcom,hawi-pcie 21 - items: 22 - enum: 23 - qcom,maili-pcie 24 - const: qcom,hawi-pcie 25 26 reg: 27 items: 28 - description: Qualcomm specific registers 29 - description: DesignWare PCIe registers 30 - description: External local bus interface registers 31 - description: ATU address space 32 - description: PCIe configuration space 33 - description: MHI registers 34 35 reg-names: 36 items: 37 - const: parf 38 - const: dbi 39 - const: elbi 40 - const: atu 41 - const: config 42 - const: mhi 43 44 clocks: 45 items: 46 - description: PCIe Auxiliary clock 47 - description: PCIe Configuration clock 48 - description: PCIe Master AXI clock 49 - description: PCIe Slave AXI clock 50 - description: PCIe Slave Q2A AXI clock 51 - description: PCIe Aggre NoC AXI clock 52 - description: PCIe Config NoC AXI clock 53 54 clock-names: 55 items: 56 - const: aux 57 - const: cfg 58 - const: bus_master 59 - const: bus_slave 60 - const: slave_q2a 61 - const: noc_aggr 62 - const: cnoc_sf_axi 63 64 interrupts: 65 minItems: 9 66 maxItems: 9 67 68 interrupt-names: 69 items: 70 - const: msi0 71 - const: msi1 72 - const: msi2 73 - const: msi3 74 - const: msi4 75 - const: msi5 76 - const: msi6 77 - const: msi7 78 - const: global 79 80 resets: 81 items: 82 - description: PCIe core reset 83 - description: PCIe link down reset 84 85 reset-names: 86 items: 87 - const: pci 88 - const: link_down 89 90required: 91 - power-domains 92 - resets 93 - reset-names 94 95allOf: 96 - $ref: qcom,pcie-common.yaml# 97 98unevaluatedProperties: false 99 100examples: 101 - | 102 #include <dt-bindings/gpio/gpio.h> 103 #include <dt-bindings/interconnect/qcom,icc.h> 104 #include <dt-bindings/interrupt-controller/arm-gic.h> 105 106 soc { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 110 pcie@1c00000 { 111 compatible = "qcom,hawi-pcie"; 112 reg = <0 0x01c00000 0 0x3000>, 113 <0 0x40000000 0 0xf1d>, 114 <0 0x40000f20 0 0xa8>, 115 <0 0x40001000 0 0x1000>, 116 <0 0x40100000 0 0x100000>, 117 <0 0x01c03000 0 0x1000>; 118 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 119 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 120 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>; 121 122 bus-range = <0x00 0xff>; 123 device_type = "pci"; 124 linux,pci-domain = <0>; 125 num-lanes = <2>; 126 127 #address-cells = <3>; 128 #size-cells = <2>; 129 130 clocks = <&gcc_pcie_0_aux_clk>, 131 <&gcc_pcie_0_cfg_ahb_clk>, 132 <&gcc_pcie_0_mstr_axi_clk>, 133 <&gcc_pcie_0_slv_axi_clk>, 134 <&gcc_pcie_0_slv_q2a_axi_clk>, 135 <&gcc_aggre_noc_pcie_axi_clk>, 136 <&gcc_cnoc_pcie_sf_axi_clk>; 137 clock-names = "aux", 138 "cfg", 139 "bus_master", 140 "bus_slave", 141 "slave_q2a", 142 "noc_aggr", 143 "cnoc_sf_axi"; 144 145 dma-coherent; 146 147 interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "msi0", "msi1", "msi2", "msi3", 157 "msi4", "msi5", "msi6", "msi7", "global"; 158 #interrupt-cells = <1>; 159 interrupt-map-mask = <0 0 0 0x7>; 160 interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 161 <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 162 <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 163 <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 164 165 interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS 166 &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, 167 <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY 168 &cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 169 interconnect-names = "pcie-mem", "cpu-pcie"; 170 171 iommu-map = <0x0 &apps_smmu 0x1000 0x1>, 172 <0x100 &apps_smmu 0x1001 0x1>; 173 174 pinctrl-0 = <&pcie0_default_state>; 175 pinctrl-names = "default"; 176 177 power-domains = <&gcc_pcie_0_phy_gdsc>; 178 179 resets = <&gcc_pcie_0_bcr>, 180 <&gcc_pcie_0_link_down_bcr>; 181 reset-names = "pci", "link_down"; 182 183 msi-map = <0x0 &gic_its 0x1000 0x1>, 184 <0x100 &gic_its 0x1001 0x1>; 185 msi-map-mask = <0xff00>; 186 187 pcie@0 { 188 device_type = "pci"; 189 reg = <0x0 0x0 0x0 0x0 0x0>; 190 bus-range = <0x01 0xff>; 191 192 #address-cells = <3>; 193 #size-cells = <2>; 194 ranges; 195 196 phys = <&pcie0_phy>; 197 wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; 198 reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; 199 }; 200 }; 201 }; 202